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We present a radio frequency self-interference (SI) canceller chip for low-power wide area network (LPWAN) basestations. To enhance the cancellation capability without necessitating unreasonable resolution, power consumption, and area, we introduce a hierarchical cancellation technique using a nested vector modulator (VM) implementation. Nesting a 7-b and two 6-b stages, a 16-b theoretical and >13-b measured resolution is obtained per tap. LPWAN channels have large group delay and group delay spread in tens of ns, and a requirement for >100 dB of analog SI cancellation. To enable large ON-chip group delay, we leverage frequency translation circuits, and in comparison to prior art, decouple impedance matching requirement from tap delay implementation to realize range/resolution from 16 ns/33 ps to 80 ns/150 ps. We demonstrate 64 dB of RF SI cancellation over 0.8-MHz bandwidth (BW) with a three-tap implementation for an LPWAN wireless channel. For more controlled environments, up to 70-dB cancellation is shown. Each tap occupies 0.21 mm2 of area and consumes 12.3 mA of current with a 1.2-V supply voltage. The whole chip occupies 1.2 mm2 and consumes 44.28 mW of power in a 65-nm CMOS process.

Varactors in RF CMOS processes often have significantly lower Q- factor ($Q_{VAR}$) than inductors and transformers at mm-wave frequencies. Direct connection of varactors to the outputs of an LC oscillator lowers overall tank Q, $Q_{T} < Q_{VAR}$ , and at the same time, increases the ratio of parasitic capacitance to total tank capacitance which limits frequency tuning range (FTR). Instead, magnetically coupling a varactor to the oscillator core using an asymmetric transformer, where the core is connected to the primary and varactor to the secondary, limits the drop in $Q_{T}$. The ratio of parasitic capacitance to total tank capacitance is also reduced. The varactor can also be operated in accumulation-mode, with a larger $Q_{VAR}$. Thus, both FTR and phase noise (PN), in comparison to traditional tanks in LC VCOs, are improved simultaneously. In this paper, two VCO prototypes are implemented in 65-nm CMOS. A 60 GHz self-mixing VCO with a VCO core operating at 20 GHz shows an FTR of 18.5%, a PN of −92.5 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −187.1 dBc/Hz. A 25 GHz VCO shows an FTR of 29.9%, a PN of −107.9 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −194.2 dBc/Hz. [ABSTRACT FROM AUTHOR]