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This article shows one of the potential applications of multiple-valued logic (MVL) for low-power data transfer in a network-on-chip (NoC). Dynamic power accounts for a large portion of the total chip interconnect power. This article combines ternary limited-weight codes (TLWCs) with quaternary transition signaling (QTS) to present a low-power bus encoding method. By this way, voltage swing and switching activity factor, the two main reasons for dynamic power consumption, are targeted. Not only does the proposed method reduce power, but it also accelerates data transmission because it compacts every four bits of information in only three ternary digits. Full details of the required components, such as a modulator, a demodulator, a quaternary flip-flop, and a quaternary repeater, are given. All circuits are simulated by Synopsys HSPICE and 32-nm CMOS technology. Then, the HSPICE results are applied to the Access Noxim simulator for NoC-level simulations. The results demonstrate that in a 3-D network with $12\times 12\times4$ nodes, the proposed MVL bus encoding decreases the total energy and the average global delay by at least 9.25% and 31.39%, respectively, compared to when binary minimal encoding is used. Finally, the proposed model reduces the effects of crosstalk noise because it eliminates rail-to-rail transitions.

ABSTRACTThis paper deals with the bridge-style circuits. They are highly efficient in terms of transistor density per unit of area. They comply with the conventional CMOS style and form a full-swing and robust structure. First, we clarify the necessary conditions under which a Boolean function can be implemented fully symmetrical. Then, it is demonstrated that it is possible to design out of functions fully symmetrical. Eventually, we show how the pull-up and pull-down networks are constructed in a bridge circuit for any three-input function which fulfils the conditions of being implemented fully symmetrical.