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The impact on set resistance distributions of phase change random access memory under different first set pulses are still not enough in-depth exploration. We discuss these impacts of 4Mb PCRAM fabricated in the 40 nm process. The set resistance distribution could be affected by the first set pulse. The optimal first set pulse amplitude is a fixed value. In order to study this phenomenon, a contrast experiment is set up to observe and analyze the array characteristics. Once the first set pulse amplitude is bigger than the optimal first set pulse amplitude, the first set pulse becomes a mixture of set and reset operation. It would affect the set resistance distribution.

Deep machine learning (DML) holds the potential to revolutionize machine learning by automating rich feature extraction, which has become the primary bottleneck of human engineering in pattern recognition systems. However, the heavy computational burden renders DML systems implemented on conventional digital processors impractical for large-scale problems. The highly parallel computations required to implement large-scale deep learning systems are well suited to custom hardware. Analog computation has demonstrated power efficiency advantages of multiple orders of magnitude relative to digital systems while performing nonideal computations. In this paper, we investigate typical error sources introduced by analog computational elements and their impact on system-level performance in DeSTIN-a compositional deep learning architecture. These inaccuracies are evaluated on a pattern classification benchmark, clearly demonstrating the robustness of the underlying algorithm to the errors introduced by analog computational elements. A clear understanding of the impacts of nonideal computations is necessary to fully exploit the efficiency of analog circuits. [ABSTRACT FROM AUTHOR]

Endurance improvement is a crucial work for phase change memory (PCM) which has always been the focus of researchers, but fewer studies concentrate on parameter optimization to improve endurance. In this paper, the correlation between the RESET condition and the endurance of PCM has been investigated systematically based on sample cells of a 4 Mb embedded PCM chip through Statistical analysis. It is evidently clear from the test results that high and narrow RESET condition can bring a significant improvement in endurance. And a new test-time-saving method for optimizing RESET condition to improve endurance is proposed. Further, the power consumption and the temperature distribution of PCM during the RESET process has been studied. The results confirmed that high heating speed and less thermal damage to the operating electrode originated from the high-narrow RESET pulse all together account for the improvement of endurance.