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Here we evaluate in-situ Ga doping of SiGe as an alternative to ex-situ ion implantation for source/drain contact formation. Si0.5Ge0.5 layers are grown on an ASM Intrepid ES high volume CVD reactor and co-doped with B and Ga. A circular transmission line measurement (CTLM) comparison of SiGe:B and SiGe:B:Ga is presented and we report a statistically significant improvement in contact resistivity with the addition of Ga. The Ti/SiGe contacts formed with the B-doped sample had an average rc ~ 9 x 10-9 O-cm2 while the best Ga/B co-doped sample yielded an average rc ~ 2.5 x 10-9 O-cm2. We also evaluate the epitaxial growth on fin patterned wafers and we are able to demonstrate high crystalline quality SiGe:Ga layers without loss of selectivity on the dielectric areas of the wafer.

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

As contact resistance becomes a bottle-neck in scaled CMOS devices, there is a need for source/drain epitaxy with maximum dopant concentrations and optimized contacting schemes. In this paper we discuss the use of highly doped Si:P layers for the Source/Drain formation in Si bulk FinFETs. We report on the macroscopic and microscopic properties of the Si:P layers and discuss the details of the microstructure and the manifestation of Phosphorus-Vacancy complexes at high Phosphorus concentrations. We analyze how a post-epi thermal budget like spike or laser annealing modifies the microstructure and leads to an enhanced P activation and diffusion. We also zoom in on some of the integration aspects of the Si:P layers and discuss the benefit of the high-P concentration for the contact resistivity and the final device performance.

Aluminum‐catalyzed epitaxial growth of silicon nanowire (SiNW) arrays was performed on Si wafer by chemical vapor deposition at 600 °C. The arrays showed a low optical total reflectance in the visible light spectrum, with a minimum of 2% around 450 nm wavelength. Following SiNW growth, dry etching of the Al catalyst was performed in situusing HCl chemistry at 600 °C. The effectiveness of aluminum etching was assessed by energy dispersive X‐ray spectroscopy, by high resolution transmission electron microscopy and by a controlled growth experiment. This SiNW array growth and subsequent catalyst dry etching opens up the possibility of an all in vacuumfabrication process of radial junction solar cells.

We present the interface state distribution at GaAs-oxide interfaces, which consist of two large peaks around mid-gap energies, one donor-like and one acceptor-like, as well as two smaller peaks closer to the band-edge energies, which are responsible for room temperature frequency dispersion in CV-curves. The latter two peaks are strongly reduced by S-passivation treatments as well as forming gas anneals, whereas the mid-gap peaks do not get affected by such treatments. It is argued that the large midgap peaks are likely caused by physical relaxation of the surface due to stress created by the oxidation, with creation of large densities (~1013 cm-2) of As and Ga vacancies at the GaAs surface. The interface state distribution of In0.53Ga0.47As-oxide interfaces is presented as well, which consists of two donor-like peaks, one large peak close to (and partly in) the valence band edge and one smaller peak around mid-gap energies. Such an interface state distribution explains the results obtained by In0.53Ga0.47As-based nMOSFET devices. Here, again, it is argued that these two peaks are likely proper to the In0.53Ga0.47As surface itself, and due to the presence of a large density of vacancies at the surface.

Here we evaluate in-situ Ga doping of SiGe as an alternative to ex-situ ion implantation for source/drain contact formation. Si0.5Ge0.5 layers are grown on an ASM Intrepid ES high volume CVD reactor and co-doped with B and Ga. A circular transmission line measurement (CTLM) comparison of SiGe:B and SiGe:B:Ga is presented and we report a statistically significant improvement in contact resistivity with the addition of Ga. The Ti/SiGe contacts formed with the B-doped sample had an average ρc ~ 9 x 10-9Ω-cm2while the best Ga/B co-doped sample yielded an average ρc ~ 2.5 x 10-9Ω-cm2. We also evaluate the epitaxial growth on fin patterned wafers and we are able to demonstrate high crystalline quality SiGe:Ga layers without loss of selectivity on the dielectric areas of the wafer.

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

As contact resistance becomes a bottle-neck in scaled CMOS devices, there is a need for source/drain epitaxy with maximum dopant concentrations and optimized contacting schemes. In this paper we discuss the use of highly doped Si:P layers for the Source/Drain formation in Si bulk FinFETs. We report on the macroscopic and microscopic properties of the Si:P layers and discuss the details of the microstructure and the manifestation of Phosphorus-Vacancy complexes at high Phosphorus concentrations. We analyze how a post-epi thermal budget like spike or laser annealing modifies the microstructure and leads to an enhanced P activation and diffusion. We also zoom in on some of the integration aspects of the Si:P layers and discuss the benefit of the high-P concentration for the contact resistivity and the final device performance.

The integration of III-V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI-GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI-GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.

We present the interface state distribution at GaAs-oxide interfaces, which consist of two large peaks around mid-gap energies, one donor-like and one acceptor-like, as well as two smaller peaks closer to the band-edge energies, which are responsible for room temperature frequency dispersion in CV-curves. The latter two peaks are strongly reduced by S-passivation treatments as well as forming gas anneals, whereas the mid-gap peaks do not get affected by such treatments. It is argued that the large midgap peaks are likely caused by physical relaxation of the surface due to stress created by the oxidation, with creation of large densities (~1013 cm-2) of As and Ga vacancies at the GaAs surface. The interface state distribution of In0.53Ga0.47As-oxide interfaces is presented as well, which consists of two donor-like peaks, one large peak close to (and partly in) the valence band edge and one smaller peak around mid-gap energies. Such an interface state distribution explains the results obtained by In0.53Ga0.47As-based nMOSFET devices. Here, again, it is argued that these two peaks are likely proper to the In0.53Ga0.47As surface itself, and due to the presence of a large density of vacancies at the surface.