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In many phase-lock loop (PLL) applications, the naturally occurring pull-in process is too slow and unreliable. Therefore, PLLs use acquisition aids to mitigate the process of locking onto the phase of some input reference signal. Commonly used acquisition aids have deficiencies with limiting effects. For voltage-controlled oscillator (VCO) sweeping, deficiencies include lock detector requirements and search rate limitations. For a charge-pump subsystem, the operated sequential phase detector (PD) is less resistant to errors than an analog multiplier PD. In order to overcome the deficiencies of common acquisition aids and improve PLL robustness to perturbations, it is proposed to use a conventional or a second order sliding mode controller (SMC/2-SMC) as an acquisition aid to provide robust finite-time phase-lock in the PLL. This improvement is achieved without the use of a lock detector, and the disabling of the acquisition aid is not necessary. The PLL aided by SMC/2-SMC is studied analytically and via simulations. A significant improvement of the PLL’s performance is demonstrated; specifically, the lock time is decreased, and the steady state phase error is reduced for a frequency ramp input. [ABSTRACT FROM AUTHOR]

In many phase-locked loop (PLL) applications, the natural pull-in mechanism is too slow and unreliable, and it must be accelerated. By adding an externally-generated ramp to its control voltage input, the PLL voltage controlled oscillator (VCO) frequency can be swept towards the input reference frequency in an attempt to speed up the pull-in process. This popular acquisition aid has a significant limitation when it is used in a second-order, Type II PLL. If the applied ramp voltage has a slope magnitude greater than (alternatively, less than) some value Rm, the PLL state can (alternatively, cannot) sweep past the desired lock point, resulting in a phase lock failure (alternatively, success). In general, the maximum sweep rate magnitude Rm can be computed by using a numerical integration-and-search procedure that is described in the PLL literature. A special case exists for a second-order, Type II PLL that incorporates a triangular-characteristic phase detector (with logic-level binary input signals). For this case, it is possible to develop an exact, closed-form expression for Rm, the main result of this paper. For a range of loop parameters most often used in applications, Rm values are computed by using the exact formula, and these are used in two ways. First, they are used to validate the previously-mentioned numerical integration-and-search procedure. Second, they are compared to maximum sweep rate values computed for a PLL that utilizes a sinusoidal phase detector to show that the triangular-phase-detector PLL can be swept significantly faster than the sinusoidal-phase-detector loop. [ABSTRACT FROM AUTHOR]