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This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. A prototype sensor comprising 640 \times 480 pixels was fabricated with a 0.13-\mum CMOS process. The results of experiments conducted indicate that the proposed ADC can achieve a conversion time of 6.4 \mus at a main clock frequency of 62.5 MHz, which is 10.2 times faster than the conventional SS ADC. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). Further, the proposed circuit employs redundancy error correction logic to calibrate the error between the coarse and fine steps. The total power consumption is 72 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital). The figure of merit (FoM) of the proposed VGA CMOS image sensor is 2.01 [e^-\ nJ]. [ABSTRACT FROM AUTHOR]

A 0.18-\mum CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of the internal circuits is reduced by 4, the power dissipation of the transceiver is much reduced. In addition, compared with a standard 16-PAM technique, the dual-mode 10-PAM technique can reduce power dissipation by 62.5%. The transmitter including a pseudo random bit sequence (PRBS) generator, multiplexers, an encoder, and an output driver achieves 10-Gb/s data-rate with 235-mW power dissipation such that the figure of merit (FOM) of the transmitter part is 23.5 mW/(Gb/s). The receiver including a flash type analog-to-digital converter (ADC), a decoder, and output drivers achieves 10-Gb/s data-rate and 10^-12 BER with 190-mW power dissipation such that FOM of the receiver part is 19 mW/(Gb/s). The proposed 10-PAM transceiver was implemented in a 0.18-\mum standard CMOS technology with 0.3\,\times\,0.8-mm^2 active area. [ABSTRACT FROM AUTHOR]