Search

Spiro-OMeTAD hole transport materials typically exhibit an amorphous state in perovskite solar cells. However, the lack of structural ordering leads to weak intermolecular interaction, inferior carrier transfer, and poor stability in devices. Herein, we developed a π-conjugation-induced short-range ordering strategy to modulate the stacking order of spiro-OMeTAD during film formation. A clear molecular ordering at the nanoscale is observed, which enhances intermolecular π–π stacking in spiro-OMeTAD and enables effective carrier extraction and favorable energy level alignment. The nanoscale-ordered spiro-OMeTAD allows the achievement of perovskite solar cells with a champion efficiency of 25.37%, surpassing devices utilizing amorphous spiro-OMeTAD (23.52%). The unencapsulated device demonstrates enhanced operational stability by retaining 98% of its initial efficiency under continuous 1 sun equivalent illumination at 60 °C for 840 h. This work establishes a significant and valid modulation concept for the stacking order of organic transport materials, paving the way for the development of efficient and stable perovskite solar cells.

Placement serves as a fundamental step in VLSI physical design. Recently, GPU-based placer DREAMPlace [1] demonstrated its superiority over CPU-based placers. In this work, we develop an extremely fast GPU-accelerated placer Xplace which considers factors at operator-level optimization. Xplace achieves around 2x speedup with better-solution quality compared to DREAMPlace. We also plug a novel Fourier neural network into Xplace as an extension. Besides, we enable Xplace to handle the detailed-routability-driven placement problem and demonstrate its superiority in terms of quality and performance. We believe this work not only proposes an extremely fast and extensible placement framework but also illustrates a possibility of incorporating a neural network component into a GPU-accelerated analytical placer. The source code of Xplace is released on GitHub.

Maze routing is usually the most time-consuming step in global routing and detailed routing. A commonly used maze routing method is to start from one pin and iteratively connect the current route to the closest unconnected pin. This method reduces the maze routing problem to multiple multisource–multidestination shortest path problems. The shortest path problem in VLSI routing has: 1) rectilinear routing directions and 2) preferably small via usage. By utilizing these two characteristics, we propose a novel parallel algorithm called GAMER to accelerate the multisource–multidestination shortest path problem for VLSI routing. GAMER decomposes the shortest path search into alternating vertical and horizontal $sweep$ operations, and two parallel algorithms are proposed to accelerate a $sweep$ operation from $O(n^{2})$ to $O(\log _{2}{n})$ on a grid graph of $n\times n$ . Several techniques of applying GAMER on irregular routing regions are also introduced. Experiments are conducted by integrating GAMER into the state-of-the-art academic global router CUGR. CUGR adopts a two-level maze routing scheme, including coarse-grained routing and fine-grained routing, and they can be accelerated by $19.85\times $ and $2.59\times $ , respectively, with GAMER, achieving an overall speedup of $2.7\times $ without quality degradation.