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Power staple insertion is an effective means to mitigate IR drop in the advanced technology process. Previous works have shown that detailed placement refinement can greatly enhance the power staple insertion rate. However, with FinFET, it is necessary to consider the drain-to-drain abutment (DDA) constraints. We note that extra source node insertion for resolving DDA violations can interfere with power staple insertion. To handle DDA constraints and optimize power staple insertion at the same time, we formulate and solve a new DDA-aware placement refinement problem in this work. Given an initial nonoverlapping placement optimized for other conventional objectives, we compute a refined placement with cell shifting subject to DDA constraints such that the number of staple insertion slots can be maximized. An effective approach is proposed that supports a nonrestricted cell displacement range during placement refinement. It provides the flexibility to adjust the displacement bound of each cell dynamically in order to resolve all DDA violations. As a result, our algorithm guarantees that a placement solution with no DDA violation can always be computed without using a large displacement range for each cell which would require much longer runtime and larger average cell displacement. In addition to cell shifting, we incorporate concurrent cell flipping to reduce the required cell displacement to satisfy the DDA constraints and to facilitate power staple insertion. The experimental results showed the effectiveness of the proposed approach.

We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given the module locations and activity information. Unlike previous works, we consider masking logic insertion and buffer insertion simultaneously, and guarantee to yield a zero-skew clock tree. Both the logical and physical information of the modules are carefully taken into consideration when determining where masking logic should be inserted. We also account for the power overhead of the control signals so that the total average power consumption of the constructed zero-skew gated clock network can be minimized. To this end, we present a recursive approach to compute the effective switched capacitance of a general gated and buffered clock network, accounting for both the clock tree's and controller tree's switched capacitance. The power consumptions of the gated clock networks constructed by our algorithm are 20 to 36% lower than those reported in the best previous work in the literature.