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InP double heterojunction bipolar transistors (InP DHBTs) are one of the key technologies considered for terahertz (THz) applications. The improvement of their frequency performance is challenging and strongly dependent on various parameters (manufacturing process, geometry, and epitaxial structure). In this article, a novel method is developed to take into account these parameters and predict the frequency performance of the technology. This approach consists of rebuilding the S-parameter matrix of the small-signal model. Elements of the small signal model are identified, and their assessment is described in detail. Once calibrated with the present state-of-the-art device features, the model shows a good agreement with the measurements. Based on this result, analysis of the emitter and base technological features are performed along with optimizations of the vertical structure. Finally, the necessary optimizations for developing a THz transistor are detailed. This works provides guidelines for technological improvement and opens the way for designing transistors operating at frequencies above a THz.

With the continuous increase in data traffic and enormous consumption of data in terms of video on demand services and cloud computing, there is an increasing demand for high speed and high sensitivity short reach receivers for passive optical networks (PON) access network which are point to multi‐point networks. Avalanche photodiodes (APD) are the standard receivers in PON networks due to their high sensitivity and low cost. However, it is currently not clear if they can provide high bandwidth above 40 GHz with good performance (gain, noise, etc.). Furthermore, standard PIN photodiodes do not provide sufficient sensitivity for PON networks. Therefore, in this article a SOA‐UTC receiver is proposed, which is a photonic integrated circuit (PIC) comprising a semiconductor optical amplifier (SOA) for optical preamplification and a high‐speed uni‐travelling‐carrier (UTC) photodiode for opto‐electronic conversion. A very high responsivity of 140 A W−1is demonstrated, with a polarization dependent loss (PDL) around 1 dB and a 3 dB bandwidth of 48 GHz, which is very promising for future PON network with 50 Gbit s−1capacity and above. A high speed and high sensitivity preamplified receiver for Passive Optical Network (PON) is proposed. We demonstrate a very high responsivity of 140 A/W, with a Polarization Dependent Loss (PDL) around 1 dB and a 3‐dB bandwidth of 48 GHz, which is very promising for future PON network with 50 Gbit/s capacity and above. W−1, with a polarization dependent loss (PDL) around 1 and a 3 dB bandwidth of 48 GHz, which is very promising for future PON network with 50 Gbit s−1capacity and above.

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the compact models allowing DTCO-efficient strategies.

This paper investigates electrical performances of two different transistor array configurations operating as 60GHz power amplifier cells. Maximum RF power gain and a maximum PAE are determined using a load-pull measurement set-up. The electrical and thermal behavior between multi-finger transistor and multi-transistor array are compared. Drawbacks and advantages of each structure are discussed and the current preference of the usage of multi-emitter structures versus multi-transistor structures is questioned.

We present an original method to implement neuro-inspired supervised learning for a synaptic array based on carbon nanotube devices. The device characteristics required to implement on chip learning within a crossbar of carbon nanotube field effect transistors (CNTFETs) as synaptic arrays were experimentally demonstrated and accurately modeled through a specific electrical compact model. We performed electrical simulations of learning for an array of 24 nanotube memory devices corresponding to a 3 input\,\times \,3 output neural layer that revealed successful learning of separable logic functions within very few epochs, even when a realistic variability of nanotube diameter was taken into account. Such a learning approach opens the way to the use of high-density synaptic arrays as generic logic blocks in configurable circuits. [ABSTRACT FROM PUBLISHER]

A new NPN-SiGe-HBT device architecture utilizing a Si3N4 strain layer is proposed. The impact of introducing a Si3N4 strain layer in the collector region on the device's electrical properties and frequency characteristics has been studied using TCAD modeling. An approximately, 8% of improvement in fT, and 5% of improvement in fMAX have been achieved in the new NPN-SiGe-HBT device's architecture in comparison with an equivalent standard conventional NPN-SiGe-HBT device. Despite of the very small decrease in the breakdown voltage BVCEO value (1%-4%), the fTxBVCE0 product enhancement is about 6% by means of strain engineering.

This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNT-FETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic. [ABSTRACT FROM AUTHOR]

A new NPN-SiGe-HBT device architecture utilizing a Si3N4strain layer is proposed. The impact of introducing a Si3N4strain layer in the collector region on the device's electrical properties and frequency characteristics has been studied using TCAD modeling. An approximately, 8% of improvement in fT, and 5% of improvement in fMAXhave been achieved in the new NPN-SiGe-HBT device's architecture in comparison with an equivalent standard conventional NPN-SiGe-HBT device. Despite of the very small decrease in the breakdown voltage BVCEOvalue (1%─4%), the fT×BVCE0product enhancement is about 6% by means of strain engineering.