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In the context of research and development activities for future hadron colliders, competitive implementations of real-time algorithms for feature extraction have been made on various forms of commercial pipelined and parallel architectures. The algorithms used for benchmarking serve for decision making and are of relative complexity; they are required to run with a repetition rate of 100 kHz on data sets of kilobyte size. Results are reported and discussed in detail. Among the commercially available architectures, pipelined image processing systems can compete with custom-designed architectures. General-purpose processors with systolic mesh connectivity can also be used. Massively parallel systems of the SIMD type (many processors executing the same program on different data) are less suitable in the presently marketed form.<>

A single-slot Fastbus master module is described. It can be used for readout and preprocessing of data that are read out from Fastbus modules, e.g. an ADC (analog-to-digital converter) system. The module consists of a 25-MHz, 32-b processor MC68030 with cache memory and memory management, a floating-point coprocessor MC68882, 4 MB of main memory, and Fastbus master and slave interfaces. The main memory is multiported and can be accessed directly by the CPU, the Fastbus, and external masters via the high-speed local bus, which is accessible by way of a connector. The Fastbus interface supports most of the standard operations in master and slave mode. An asynchronous state machine converts the microprocessor transfer protocol to Fastbus operations and thus the MC68030 operates as a native processor on the Fastbus. Due to the architecture chosen, each Access of the processor to the Fastbus space causes the execution of a complete Fastbus transfer sequence, e.g. a primary address cycle, a secondary address cycle, and a data cycle. This simplifies the programming of the Fastbus master considerably.<>

A programmable trigger processor for the recognition of Cerenkov rings in a RICH (ring image Cerenkov) counter is described. It identifies open electron pairs and suppresses close conversion and Dalitz pairs within 20 mu s. More generally, the system can be used for correlating pixel images with pattern masks in order to locate all relatively well defined patterns of a certain type. The trigger processor consists of a systolic processor array of 160*176, i.e. 28160 identical processing elements (PEs) that filter out open electron pairs, and a pseudo adder array that determines whether there was at least one such pair. Ring identification is done by a two-dimensional correlation of the input image with a circle, yielding the probability of finding circles at certain locations. All PEs run synchronously at a clock frequency of 30 MHz. The total computing power therefore amounts to 844800 million operations/s, where a typical operation is the combination of a 6-b addition and a shift.<>

A modular Fastbus ADC (analog-to-digital converter) system for data acquisition in high-energy and nuclear physics experiments with a high number of channels is described. One ADC module occupies two Fastbus slots and provides 64 channels. Each module consists of an analog preprocessing part, the ADC section, and the Fastbus slave interface logic. Each channel can individually be stuffed with TVCs (time-to-voltage converters), CVCs (charge-to-voltage converters), or PVCs (pulse height-to-voltage converters). All channels are multiplexed to a single ADC unit. ADCs with a conversion time of less than 1 mu s and a data width of up to 16 b can be used (2.7 mu s/12 b currently). The differential nonlinearity can be eliminated by a statistical correction. The slave interface logic of the ADC module supports most of the standard Fastbus operations. The Fastbus ADC module is currently running as a prototype. All functions have been tested successfully.<>

Twenty-one patients with perforation of the oesophagus were diagnosed and treated at the University Central Hospital of Turku in 1960-1969. Fourteen of them were instrumental and seven spontaneous perforations. In the cases of instrumental perforation the rupture generally occurred in connection with dilatation of lye stricture. In instrumental perforations the diagnosis was mostly delayed and treatment conservative. The mortality rate was 14% (2/14). In perforations caused by lye stricture conservative therapy led to a good result for the fixation of the environment and adhesions limited the spread of a mediastinal infection. In contrast, radical surgery should be the aim in other perforations, especially cases with residual distal obstruction. Two of the seven patients with spontaneous perforation died. Our results substantiate the view that early closure of spontaneous perforation should be aimed at. Although two patients were cured with pleural canalization alone, another two patients treated by the same method died. The three patients whose primary therapy consisted of thoracotomy and closure of the rupture recovered.

A case of false popliteal aneurysm caused by an osteochondroma of the femur in a 13 year old boy is reported with angiographic findings.

The Enable Machine is a systolic 2nd level trigger processor for the transition radiation detector (TRD) of ATLAS/LHC. It is developed within the EAST/RD-11 collaboration at CERN. The task of the processor is to find electron tracks and to reject pion tracks according to the EAST benchmark algorithm in less than 10 /spl mu/s. Track are identified by template matching in a (/spl phi/,z) region of interest (RoI) selected by a 1st level trigger. In the (/spl phi/,z) plane tracks of constant curvature are straight lines. The relevant lines form mask templates. Track identification is done by histogramming the coincidences of the templates and the RoI data for each possible track. The Enable Machine is an array processor that handles tracks of the same slope in parallel, and tracks of different slope in a pipeline. It is composed of two units, the Enable histogrammer unit and the Enable z//spl phi/-board. The interface daughter board is equipped with a HIPPI-interface developed at JINR/Dubna, and Xilinx 'corner turning' data converter chips. Enable uses programmable gate arrays (XILINX) for histogramming and synchronous SRAMs for pattern storage. With a clock rate of 40 MHz the trigger decision time is 6.5 /spl mu/s and the latency 7.0 /spl mu/s. The Enable machine is scalable in the RoI size as well as in the number of tracks processed. It can be adapted to different recognition tasks and detector setups. The prototype of the Enable Machine has been tested in a beam time of the RD6 collaboration at CERN in October 1993.<>