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Chemical reaction networks based on catalysis, degradation, and annihilation may be used as building blocks to construct a variety of dynamical and feedback control systems in Synthetic Biology. DNA strand-displacement, which is based on DNA hybridisation programmed using Watson-Crick base pairing, is an effective primitive to implement such reactions experimentally. However, experimental construction, validation and scale-up of nucleic acid control systems is still significantly lagging theoretical developments, due to several technical challenges, such as leakage, crosstalk, and toehold sequence design. To help the progress towards experimental implementation, we provide here designs representing two fundamental classes of reference tracking control circuits (integral and state-feedback control), for which the complexity of the chemical reactions required for implementation has been minimised. The supplied ‘minimally complex’ control circuits should be ideal candidates for first experimental validations of nucleic acid controllers.

In the design of sigma-delta modulators ($\Sigma \Delta $ Ms), different variables need to be optimized together in order to maximize the performance. This design task has the added difficulty of dealing with the non-linear behavior of the quantizer. Although a linearized model of the quantizer can be used, this may result in significant discrepancies between the predicted and actual behavior of the $\Sigma \Delta \text{M}$. To better predict the behavior of a given design, we propose a design methodology for $\Sigma \Delta $ Ms based on a genetic algorithm (GA) that uses both linear equations and simulations. In order to reduce the computation time, the design solution is initially evaluated using equations and only if the performance is deemed good enough, it is subjected to a more refined simulation. This more precise simulation takes into account thermal noise, finite output swing, and gain (among other non-idealities) of the building blocks of the modulator. Moreover, Monte Carlo (MC) analyses are performed during the optimization in order to assess the sensitivity to component variations of the solutions. In order to demonstrate the validity and robustness of the proposed optimization methodology, several $\Sigma \Delta $ Ms designs are presented, together with the corresponding measured results. [ABSTRACT FROM AUTHOR]

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators ($\Delta \Sigma $ Ms) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the $\Delta \Sigma \text{M}$ loop filter. A third-order CT $\Delta \Sigma \text{M}$ is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS $\Delta \Sigma \text{M}$ occupies only $0.013~\mathrm {mm^{2}}$ , dissipates 256 $\mu \text{W}$ from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a $\mathrm {FoM_{Schreier}}$ of 175.1 dB. [ABSTRACT FROM AUTHOR]

This paper presents a MASH \Sigma \Delta \textM using only passive integrators and simple differential pairs as low-gain blocks. Instead of high-gain power hungry op-amps it uses more processing gain from the comparator (1-bit quantizer) as a part of the loop gain. The proposed approach allows the design of a continuous-time, 2–1 MASH \Sigma \Delta \textM in a 65-nm CMOS technology occupying an area of just 0.027 mm2. Measurement results show that the modulator achieves a peak SNR/SNDR of 76/72.2 dB and a DR of 77 dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW with 1 V supply. The proposed \Sigma \Delta \textM achieves a Walden figures of merit (FoM) of 23.6 fJ/level and a Schreier FOM of 170 dB. [ABSTRACT FROM AUTHOR]

This paper presents an efficient numerical methodology to obtain the frequency response of switched-capacitor filters based on the circuits' differential equations. This methodology uses a non-hierarchical approach in which the non-ideal effects of the transistors (in the switches and in the amplifier) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. The accuracy is demonstrated by comparing the results obtained using the proposed methodology with those obtained using transient electrical simulation results for three different SC circuits: a first order SC passive filter, a second order SC lowpass filter, and a second order SC bandpass filter, showing that the results are in good agreement with the more time consuming electrical simulation of the circuits. [ABSTRACT FROM PUBLISHER]

This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks. A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP’s data memory. The scheduling of load/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60× and 1.18× for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.