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This paper presents for the first time a fully integrated galvanic isolation interface in a GaN technology. It is based on planar micro-antennas and chip-to-chip communication with an on-off keying-modulated RF carrier. This approach can achieve high isolation rating and high common-mode transient immunity by properly setting the distance between chips. The interface provides the isolation channel for a main driver/power switch and the one for the control feedback of the dc-dc converter providing the isolated power supply. Driver and power control channels adopt an RF carrier of 2 GHz and 1.2 GHz, which are modulated by a pulse width modulated signal of 2 MHz and 0.5 MHz, respectively. The interface includes a continuously operating offset compensation approach, which overcomes not only the strong variations due to the large process tolerances of the GaN technology, but also offset drifts due to temperature variations. An accurate pulse width modulated signal with a large duty cycle variation in both channels was achieved. The isolation interface adopts a 6-V power supply, which delivers a quiescent current of 6.3 mA and 7.5 mA to the driver and power control channels, respectively, assuming a signal with a duty cycle of 50%.

A bulk-driven operational transconductance amplifier (OTA) suitable for ultralow-power and ultralow-voltage applications is described. The amplifier exploits local positive feedback in the first stage to increase its transconductance. The OTA entails a single Miller capacitor for frequency compensation, thus saving area occupation and improving frequency performance. As a distinctive feature of the proposed solution, the OTA is stable for capacitive loads higher than 5 pF. Implemented in a 65-nm standard CMOS technology, the proposed solution occupies an area of $10.6 \cdot 10^{-3}$ mm2 and is powered from 0.3 V, with a total quiescent current equal to $8.5 \mu \text{A}$ . Experimental measurements show a gain–bandwidth (GBW) product of 1.65 MHz (0.81 MHz) with a phase margin (PM) equal to 70° (71°) when driving a 50-pF (150-pF) load, featuring the best figures of merit compared to other multistage sub-1-V OTAs in the literature.

This paper presents a CMOS operational transconductance amplifier (OTA), suitable for sub-1-V supply applications, whose (input) common-mode voltage can be set to ( V\mathrm {\mathbf {DD}}+V\mathrm {\mathbf {SS}}) /2 thanks to two combined techniques applied to the differential pair, namely, threshold voltage lowering and elimination of the tail current generator. Both techniques are implemented through a single common-mode feedback loop, which embeds the shared bulk terminal of the pair. In contrast to other low-voltage approaches employing bulk driving, the proposed OTA is driven from the gate terminals and exploits only MOS transistors in strong inversion. Therefore, effective values of dc gain, gain bandwidth, and noise are found, suitable for high-accuracy switched-capacitor applications. Using a standard 0.35- \mu \textm technology with nominal MOS transistors threshold around 0.7 V, a 0.9-V OTA with 0.45-V analog ground was designed and successfully tested. The measured gain and unity gain frequency were 65 dB and 1 MHz with phase margin of 60° for a capacitive load of 10 pF. [ABSTRACT FROM AUTHOR]

A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of 19.8\cdot 10^-3\ \textmm^2 and is powered from 0.7 V with a standby current consumption of around 36 \mu\textA. DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art. [ABSTRACT FROM PUBLISHER]

This paper introduces a new effective single-Miller capacitor compensation topology for three-stage amplifiers with very large capacitive loads, realized through an active-feedback capacitor together with an inner half-feedforward stage. Moreover, an optimized design strategy which profitably exploits the two left half-plane zeros is presented. To improve the amplifier large signal transient response, the topology also includes an external feedforward path, that only marginally affects the frequency compensation, and a novel slew-rate enhancer section. To validate the solutions presented, a three-stage OTA driving a 10-nF load has been designed and implemented in a standard 0.35-\mu\textm CMOS technology. The amplifier occupies less than 0.003-mm2 of die area, provides 2.7-MHz gain-bandwidth product and 0.55-V/\mu\texts average slew-rate, while consuming only 25-\mu\textA quiescent current. [ABSTRACT FROM AUTHOR]

Designing four-stage operational transconductance amplifiers (OTAs) is often considered a challenging task mainly because of the required non trivial frequency compensation procedure. In this study, starting from the simplest architecture (a differential stage cascaded by three common source stages) a high-performance OTA is demonstrated, outperforming all the (few) previous implementations. Thanks to the frequency compensation scheme and to the adoption of a slew-rate enhancer section, the solution is able to drive large capacitive loads as high as 1 nF, rivaling in terms of bandwidth and speed even with three-stage counterparts, traditionally credited to be better because of the less number of high-impedance nodes. The solution, fabricated in a 0.35-\mum technology, occupies 0.014-mm^2 with DC consumption of 170 \muW. It also achieves nearly 3-MHz gain bandwidth product while driving the 1-nF load with less than 0.5-\mus 1% settling time. [ABSTRACT FROM AUTHOR]

A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented. The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed a CMOS OTA in a 0.35-\mum technology that occupies only 4.4\cdot 10^-3\ mm^2, is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 mV/\mus with the 200 pF load. Comparison with prior art shows an improvement factor in the figures of merit higher than 5. [ABSTRACT FROM AUTHOR]

The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensitivity and measure accuracy irrespectively of the input parasitic capacitance. Therefore, the main limitation of all previous current-mode techniques is nearly eliminated. Besides, as an additional distinctive aspect, the proposed solution is suitable for both linear- and hyperbolic-type capacitive sensors. To validate the idea an interface circuit was designed in a 65-nm CMOS technology powered from a 2.5-V supply and dissipating 88- μA standby current. Measurements show that relative capacitive sensor variations up to ± 900 fF ( ± 100% of the nominal value) even in presence of a large parasitic capacitance of 2.5 pF are detected in less than 1 μs with a sensitivity of about 5 nA/fF and with an relative error lower than ± 1.5%, without requiring digital calibration. [ABSTRACT FROM AUTHOR]

A high-performance buffer amplifier topology for liquid crystal display drivers is presented. The proposed amplifier achieves fast driving performance and offers a rail-to-rail common-mode input range. Enhanced slewing and settling capabilities are achieved through a novel output stage performing dual-path push-pull operation. No additional biasing network is required to set the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself, without additional power dissipation. Experimental results demonstrate that the suggested buffer can drive a 1000-pF capacitive load with a 5.7\-V/\mus slew-rate and a 0.71\-\mus settling time, while drawing 32\-\muA overall quiescent current from a 5-V power supply. [ABSTRACT FROM PUBLISHER]

We present a DC-DC converter for photovoltaic (PV) applications that is suitable for distributed power conversion obtained by transferring part of the electronics from the inverter to the module. The proposed circuit implements a high-efficiency four-phase interleaved boost converter employing relatively low-valued inductive and capacitive components. Its compact realization is made possible thanks to the innovative design of a dedicated integrated circuit (IC) embedding the power MOS switches and performing the converter control section as well as the Maximum Power Point Tracking (MPPT) algorithm. The solution is designed for a maximum delivered power of 300 W and to work with an MPPT voltage between 9 V and 36 V, with maximum allowed panel current of 9 A. The area of the complete printed-circuit board is 4 cm\,\times\,7 cm. Experimental measurements show that the average power conversion efficiency is between 93% and 99% and that the MPPT efficiency is always greater than 99.7%. [ABSTRACT FROM PUBLISHER]

The gain-bandwidth conflict is one the most important limitations of high gain feedback amplifiers. In this tutorial paper we will discuss in a unified manner the most important approaches aimed to design amplifiers with a constant closed-loop bandwidth. Advantages and drawbacks are evidenced and new potential solutions are also formulated. [ABSTRACT FROM PUBLISHER]

A mixed-signal universal architecture able to emulate the behavior of an n-port analog circuit is presented. It exploits second-generation current conveyors as analog input/output blocks and a field programmable gate array circuit as digital processing element. A prototype is also discussed for the specific case of a two-port network synthesis and experimental results in agreement with expected ones are provided. [ABSTRACT FROM AUTHOR]

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-µm CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included. [ABSTRACT FROM AUTHOR]

This paper proposes a theoretical approach for evaluating distortion in the frequency domain of three-stage amplifiers adopting two commonly used compensation techniques, namely the nested Miller (NM) and the reversed NM. The analysis is based on appropriate amplifier modeling and on the assumption that the nonlinearity generated by each stage is static. Calculations are thus greatly simplified avoiding complex methods based on the Volterra series. Only dominant contributions need to be taken into account, thereby highlighting those mechanisms generating distortion and their features in the frequency domain. Moreover, the adopted approach provides useful design guidelines and explains why the NM compensation technique allows generally better linearity performance at low frequency and why the reversed NM is best suited to high frequencies. Simulation results with Spectre on two transistor-level CMOS circuits are also provided and found to be in very good agreement with expected results. [ABSTRACT FROM AUTHOR]

A simple methodology to evaluate harmonic distortion in the frequency domain for circuits and systems made up of a nonlinear high-gain path with a nonlinear feedback network is presented. The approach provides compact closed-form expressions which constitute a direct extension of the classic ones valid at dc. The result improve our understanding of nonlinear frequency behavior in general feedback circuits and can even be used in manual design. The accuracy of the equations obtained was evaluated by comparison with computer simulations and measurements on an example circuit. Simulated and experimental data highly agree with the theoretical model. [ABSTRACT FROM AUTHOR]

Riassunto Gli AA. studiano il comportamento elettroforetico di 370 diabetici di cui 175 senza complicanze, 131 con complicanze varie e 74 con associazioni morbose diverse. Dall'insieme dei risultati ottenuti risulta che le complicanze diabetiche vere e proprie determinano, ad eccezione del coma, modificazioni proteiche modeste. Nelle associazioni morbose si osservano le modificazioni proteiche rilevate in tali malattie nei soggetti non diabetici.

Riassunto Gli AA., dopo aver accennato all'importanza del fegato nel ricambio glicidico in generale e nel diabete in particolare, fanno una rapida rassegna bibliografica dei dati relativi allo spinoso problema degli eventuali rapporti correlativi esistenti tra lesioni istologiche e alterazioni funzionali del fegato nei diabetici. Essi, dopo aver esposti e commentati i dati derivati da una ricerca personale su 32 diabetici, concludono nel senso che tra lesioni istologiche e turbe funzionali epatiche, non sempre esiste possibilità di correlazione, specie quando lo studio si conduce in un gruppo non omogeneo di ammalati o si considerano i casi singolarmente.

A response by Salvatore Pennisi, Giuseppe Scotti and Alessandro Trifiletti to a letter to the editor about their article "Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers" in the September 9, 2011 issue is presented.