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Active power decoupling (APD) is a highly adopted technique for compact and reliable single-phase inverters to eliminate the undesired ac power drawn from the dc port. Typical operation of APD circuits requires the use of additional sensors measuring APD states to ensure proper decoupling. The additional voltage and current sensors add to system cost and hardware design complexity. This article proposes a sensorless control approach that provides proper control of the APD without the use of additional sensors. The proposed predictive power decoupling control is analyzed together with the operating principle of the APD, and two types of error correctors are introduced to improve the control accuracy and reduce the reliance on the circuit component parameters. The proposed approach provides equally good power decoupling performance compared to traditional sensor-based control strategies while improving the dynamic response. The proposed approach is experimentally verified using a 30–60 V parallel APD circuit and 200 W microinverter hardware prototype.

This article proposes a multilevel 24-sided polygonal voltage space vector structure (VSVS), eliminating lower order harmonics up to 19th order and suppressing higher order harmonics in motor phase voltage throughout the modulation range. Unlike switched average vectors in literature, the proposed scheme generates real active vectors that have the advantage of less switching frequency operation. The proposed VSVS consists of two concentric polygons divided into similar triangles resulting in a simple modulation algorithm. Instantaneous error in phase voltage reduces due to the multilevel property of the proposed VSVS. The proposed scheme extends the dc bus utilization and linear range of operation. The proposed scheme is implemented on an open-end winding induction motor fed with primary and secondary inverters from either end. This article also presents a modulating wave-based method to compute nearest vector timings using sampled reference waves only. Unlike conventional methods, the proposed timing calculation method does not require trigonometric operations, sorting algorithms, and iterative search algorithms. Experimental verification of the proposed scheme is performed to validate the concept. Switching loss and Fourier analysis comparison with some existing schemes is also presented.

An inverter circuit to generate a 13-level 24-sided polygonal voltage space vector structure (VSVS) comprised of 288 real active vectors and a zero vector is proposed in this article. The proposed scheme eliminates lower order harmonics up to 19th order and suppresses higher order harmonics from motor phase voltage in the full modulation range. The 48-step operation of the proposed scheme highly improves phase voltage quality at full speed. The dc bus utilization of the proposed scheme is improved to 99.42% compared to 90.6% multilevel hexagonal VSVS. The proposed topology has inherent capacitor balancing in every sampling interval at any loading condition using pole voltage redundancies. Multilevel property of the proposed scheme reduces instantaneous error in phase voltage compared to two-level 24-sided polygonal VSVS. Generation of real active vectors reduces instantaneous error in phase voltage and reduces switching frequency compared to switched average techniques existing in the literature. Fault-tolerant feature of the proposed scheme improves the availability of the drive system. Experimental results are provided to validate the steady-state operation, capacitor balancing, transient performance, and fault-tolerant capability of the proposed scheme. The comparison of switching loss and harmonic performance of the proposed scheme is performed with existing topologies.