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Computing systems working in harsh environment is prone to suffer from radiation-induced soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are the major reliability issue for circuits fabricated with nanoscale technology nodes. In this paper, we proposed a low-cost SET and SEU error tolerant flip-flop (SETU-TOFF). Based on the traditional flip-flop, two high-level sensitive redundant latches are added to latch the input data at different times, and a voter is designed for the correct output. It removes the timing overhead of temporal redundancy from the critical path of the systems. Comparing with the existing designs presented in literatures, SETU-TOFF has comprehensive fault tolerant capability with lower overheads; moreover, it doesn’t increase significant latency of the flip-flops. We use the SETU-TOFF cells to protect a pipeline of an OpenRISC microprocessor. Fault injection simulations show that SETU-TOFF can achieve 100% protection for the pipeline with negligible performance loss; additionally, it can detect and correct errors in real time without extra system control logic and clocks for errors recovery. [ABSTRACT FROM AUTHOR]

A pulse shielded SRAM cell is proposed for increasing the SEU performance which is used in block RAM (BRAM) and configuration memory of FPGAs. The pulse current from an incident particle is shielded because of the increasing single event response time for a SRAM cell. The SEU performance is verified by the 64k SRAMs with SEU threshold improving from 25 MeV , cm2 , mgv to 45 MeV , cm2 , mg-1at only 21.3% additional cost of the SRAM cell area. By adopting the pulse shielded SRAM cell and radiation hardened process, the 300,000 - gate FPGA possesses radiation features： SEU threshold higher llian 37. 3 MeV , cm2 , mg-1 ； SEL threshold higher than 99. 8 MeV , cm2 , mg -1 and total dose tolerance higher than 200 krad(Si) respectively. [ABSTRACT FROM AUTHOR]