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Dedicated hardware is required to efficiently execute the highly resource-demanding modern artificial neural networks (ANNs). The high complexity of ANN systems has motivated the use of high-level synthesis (HLS) tools, which increase design abstraction. Higher abstraction reduces the implementation of field-programmable gate array (FPGA) hardware details visible to the designer, making an accurate reliability evaluation challenging. When ANN hardware accelerators are used in safety-critical systems, reliability becomes paramount, and to have a realistic reliability evaluation, physical fault injection, such as beam testing, is mandatory. Existing reliability analysis approaches focus on specific ANN hardware accelerator designs, but when HLS tools are used, the tool flow and design decisions can impact reliability. Therefore, we evaluate the error rate of ANN hardware accelerators generated by HLS tools under high-energy neutrons and explore the impact of HLS parameters on reliability. Our results show that by tweaking hardware parameters, such as the reuse of resources, it can increase the error rate linearly. Furthermore, the generated ANN hardware accelerator with the best tradeoff of area and execution cycles can deliver $15\times $ more correct executions than the least optimized one, despite its increased error rate.

Artificial intelligence (AI) on the edge has emerged as an important research area in the last decade to deploy different applications in the domains of computer vision and natural language processing on tiny devices. These devices have limited on-chip memory and are battery-powered. On the other hand, neural network (NN) models require large memory to store model parameters and intermediate activation values. Thus, it is critical to make the models smaller so that their on-chip memory requirements are reduced. Various existing techniques like quantization and weight-sharing reduce model sizes at the expense of some loss in accuracy. We propose a lossless technique of model size reduction by focusing on the sharing of exponents in weights, which is different from the sharing of weights. We present results based on generalized matrix multiplication (GEMM) in NN models. Our method achieves at least a 20% reduction in memory when using Bfloat16 and around 10% reduction when using IEEE single-precision floating point, for models, in general, with a very small impact (up to 10% on the processor and less than 1% on FPGA) on the execution time with no loss in accuracy. On specific models from HLS4ML, about 20% reduction in memory is observed in single precision with little execution overhead.

The reliability evaluation of deep neural networks (DNNs) executed on graphic processing units (GPUs) is a challenging problem, since the hardware architecture is highly complex, and the software frameworks are composed of many layers of abstraction. While software-level fault injection is a common and fast way to evaluate the reliability of complex applications, it may produce unrealistic results, since it has limited access to the hardware resources, and the adopted fault models may be too naive (i.e., single and double bit flips). Contrarily, physical fault injection with neutron beam provides realistic error rates but lacks fault propagation visibility. This article proposes a characterization of the DNN fault model combining both neutron beam experiments and fault injection at the software level. We exposed GPUs running general matrix multiplication (GEMM) and DNNs to beam neutrons to measure their error rate. On DNNs, we observe that the percentage of critical errors can be up to 61% and show that the error correction code (ECC) is ineffective in reducing critical errors. We then performed a complementary software-level fault injection, using fault models derived from register-transfer level (RTL) simulations. Our results show that by injecting complex fault models, the version 3 of you only look once (YOLOv3) misdetection rate is validated to be very close to the rate measured with beam experiments, which is $8.66\times $ higher than the one measured with fault injection using only single-bit flips.

Heterogeneous (HE) multicore platforms, such as ARM big.LITTLE, are widely used to execute embedded applications under multiple and contradictory constraints, such as energy consumption and real-time (RT) execution. To fulfill these constraints and optimize system performance, application tasks should be efficiently mapped on multicore platforms. Embedded applications are usually tolerant to approximated results but acceptable quality of service (QoS). Modeling-embedded applications by using the elastic task model, namely, imprecise computation (IC) task model, can balance system QoS, energy consumption, and RT performance during task deployment. However, state-of-the-art approaches seldom consider the problem of IC task deployment on HE multicore platforms. They typically neglect task migration, which can improve the solutions due to its flexibility during the task deployment process. This article proposes a novel QoS-aware task deployment method to maximize system QoS under energy and RT constraints, where the frequency assignment (FA), task allocation (TA), scheduling, and migration are optimized simultaneously. The task deployment problem is formulated as mixed-integer nonlinear programming. Then, it is linearized to mixed-integer linear programming to find the optimal (OPT) solution. Furthermore, based on the problem structure and problem decomposition, we propose a novel heuristic (HEU) with low computational complexity. The subproblems regarding FA, TA, scheduling, and adjustment are considered and solved in sequence. Finally, the simulation results show that the proposed task deployment method improves the system QoS by 31.2% on average (up to 112.8%) compared to the state-of-the-art methods and the designed HEU achieves about 53.9% (on average) performance of the OPT solution with a negligible computing time.

Multicore architectures have been used to enhance computing capabilities, but the energy consumption is still an important concern. Embedded application domains usually require less accurate, but always in-time, results. Imprecise computation (IC) can be used to divide a task into a mandatory subtask providing a baseline quality of service (QoS) and an optional subtask that further increases the baseline QoS. This paper aims at maximizing the system QoS by solving task mapping and dynamic voltage and frequency scaling for dependent IC-tasks under real-time and energy constraints. Compared with the existing approaches, we consider the joint-design problem, where task-to-processor allocation, frequency-to-task assignment, task scheduling, and task adjustment are optimized simultaneously. The joint-design problem is formulated as an $\mathcal {NP}$ -hard mixed-integer non-linear programming, and it is safely transformed to a mixed-integer linear programming (MILP) without performance degradation. Two methods (basic and accelerated version) are proposed to find the optimal solution to an MILP problem. They are based on problem decomposition and provide a controllable way to trade off the quality of the solution and the computational complexity. The optimality of the proposed methods is proved rigorously, and the experimental results show reduced computation time (23.7% in average) compared with the existing optimal methods.

In embedded systems using fixed-point arithmetic, converting applications into fixed-point representations requires a fast and efficient accuracy evaluation. This paper presents a new analytical approach to determine an estimation of the numerical accuracy of a fixed-point system, which is accurate and valid for all systems formulated with smooth operations (e.g., additions, subtractions, multiplications and divisions). The mathematical expression of the system output noise power is determined using matrices to obtain more compact expressions. The proposed approach is based on the determination of the time-varying impulse-response of the system. To speedup computation of the expressions, the impulse response is modelled using a linear prediction approach. The approach is illustrated in the general case of time-varying recursive systems by the Least Mean Square (LMS) algorithm example. Experiments on various and representative applications show the fixed-point accuracy estimation quality of the proposed approach. Moreover, the approach using the linear-prediction approximation is very fast even for recursive systems. A significant speed-up compared to the best known accuracy evaluation approaches is measured even for the most complex benchmarks. [ABSTRACT FROM AUTHOR]

Wireless sensor networks (WSN) is a new and very challenging research field for embedded system design automation. Engineering a WSN node hardware platform is known to be a tough challenge, as the design must enforce many severe constraints, among which energy dissipation is by far the most important one. WSN node devices have until now been designed using off-the-shelf low-power microcontroller units (MCUs), even if their power dissipation is still an issue and hinders the widespread use of this new technology. In this work, we propose a complete system-level flow for an alternative approach based on the concept of hardware microtasks, which relies on hardware specialization and power gating to drastically improve the energy efficiency of the computational/control part of the node. Our case study shows that power savings between one to two orders of magnitude are possible w.r.t. MCU-based implementations.

One of the most important stages of floating-point to fixed-point conversion, is the evaluation of the fixed-point specification accuracy. This evaluation is required to optimize the data word-length according to accuracy constraints. Classical methods for accuracy evaluation are based on fixed-point simulations but they lead to very long optimization times. A new method based on an analytical approach is presented for the case of linear-time-invariant (LTI) systems. The use of this method in data word-length minimization processes reduces significantly the optimization time compared to simulation based methods. Our approach allows the automatic determination of the signal-to-quantization-noise-ratio (SQNR) expression at the system output according to the fixed-point data format. This method is valid for recursive and non-recursive LTI systems and takes account of the quantization modes (truncation or rounding). The theoretical concepts and the different methodology stages are explained. Then, the ability to efficiently evaluate the fixed-point specification accuracy is demonstrated through examples. [ABSTRACT FROM AUTHOR]

Digital signal processing applications are specified with floating-point data types but they are usually implemented in embedded systems with fixed-point arithmetic to minimise cost and power consumption. Thus, methodologies which establish automatically the fixed-point specification are required to reduce the application time-to-market. In this paper, a new methodology for the floating-to-fixed point conversion is proposed for software implementations. The aim of our approach is to determine the fixed-point specification which minimises the code execution time for a given accuracy constraint. Compared to previous methodologies, our approach takes into account the DSP architecture to optimise the fixed-point formats and the floating-to-fixed-point conversion process is coupled with the code generation process. The fixed-point data types and the position of the scaling operations are optimised to reduce the code execution time. To evaluate the fixed-point computation accuracy, an analytical approach is used to reduce the optimisation time compared to the existing methods based on simulation. The methodology stages are described and several experiment results are presented to underline the efficiency of this approach.

Abstract: The implementation of adaptive filters with fixed-point arithmetic requires computation quality evaluation. The accuracy may be determined by computing the global quantization noise power at the system output. In this paper, a new model for evaluating analytically the global noise power in LMS-based algorithms is presented. Thus, the model is developed for LMS and NLMS algorithms. The accuracy of our model is analyzed by simulations. [Copyright &y& Elsevier]