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This work presents the development of a dual-layer proton irradiation profile to decrease the fluence required to create a thermally stable localized high-resistivity silicon (HR-Si) substrate for on-chip passive component enhancement and to create a guard band to suppress noise coupling. Additional irradiation was done on the Si-SiO2 interface to prevent conductive layer formation and reduce the main irradiation’s fluence requirement. The thermally stable dual-layer profile was optimized experimentally by applying several interface and main irradiation fluence combinations to the on-chip inductor and comparing the quality factor before and after annealing. The optimum total fluence found for the dual-layer profile was ${4} \times {10}^{{14}}$ cm−2 with a measured mask-edge margin distance of ${22}~\mu $ m, corresponding to 60% fluence reduction and 56% margin reduction compared to conventional proton irradiation with 1015-cm−2 fluence. Adding a 20- $\mu $ m-thick guard band formed by dual-layer proton irradiation between two circuits introduced 5-dB noise coupling suppression at 1 GHz, with a further 2.5-dB increase every time the thickness was doubled.

This article introduces a low-power radiation-hardened $Ka$ -band CMOS phased-array receiver for the low Earth orbit (LEO) small satellite communication system. As the available solar panel area limits the power consumption of the receiver, a multi-coupling common-gate (CG) low noise amplifier (LNA) with current-sharing topology and built-in 180° phase shifter is proposed in this work to solve the power issue. The multi-coupling LNA utilizes three coupling inductors to reduce the input matching impedance with a smaller input CMOS transistor size. After implementing the proposed technique, a single beamformer realized a 3.4-mW typical power consumption compared with the conventional works with 17.3–195-mW power consumption. The receiver with magnetic-tuning phase shifter (MTPS) has 0.06-dB/Mrad gain and 0.4°/Mrad phase degradations and is the lowest reported root-mean-square phase and gain errors due to radiation. The proposed receiver achieves −22-dBm IIP3 with a 3.8-dB noise figure. The required on-chip area for each element is only 0.2 mm2. In the over-the-air (OTA) measurement, digital video broadcasting-second generation extension (DVB-S2x) standard modulated signals of up to 256 amplitude phase shift keying (APSK) can be supported by the proposed large array modules. This work realizes −33.2-dB error vector magnitude (EVM) and 12.8-Gb/s link speed with 1.6-GHz channel bandwidth. The measured beam pattern can cover radiated angle from −50° to +50° with lower than −10-dBc sidelobe level. Because of the proposed multi-coupling LNA and MTPS, a low-power radiation-hardened phased-array receiver for small LEO satellites can be achieved in this work.

This article proposes a time-mode-modulation (TMM) digital quadrature power amplifier (PA), which can realize high power efficiency at power back-off (PBO) by applying the 1-bit delta–sigma modulator (DSM) and hybrid finite impulse response (FIR) filter. The 1-bit DSM and digital mixer encode the multi-bit baseband $I/Q$ input signal into a 1-bit signal for on/off controlling the 1-bit PA to realize the TMM operation. Capacitor arrays are not required in the proposed PA, and redundant power dissipation on charging the capacitor array in conventional switched capacitor PAs (SCPAs) is avoided. Furthermore, a hybrid FIR filter comprising a two-tap digital FIR filter and a two-tap transformer (XFMR) combined semi-digital FIR filter suppresses the DSM quantization noise (QN) to avoid efficiency degradation. The XFMR combined semi-digital FIR filter is insensitive to mismatches, which maintains the high linearity of the 1-bit TMM PA. The proposed TMM PA is fabricated in 65-nm CMOS. Without digital pre-distortion (DPD), it achieves 26.4% power-added efficiency (PAE) with 40-MSymbol/s 64-quadrature amplitude modulation (QAM) signal and 20.9% PAE with 20-MSymbol/s 256-QAM signal at 2.6 GHz.

A sub-THz (88–136 GHz) full-duplex (FD) phased-array transceiver (TRX) integrating an RF self-interference (SI) canceller with differential feeding FD antennas is presented in this work. The LO phase generation chain controls differential transmitter outputs for the phased-array operation. The differential feeding FD antenna with differential pairs of chips achieves over 35-dB SI suppression. The SI suppression is improved by 20 dB when the SI canceller is turned on. Without any digital-domain SI cancellation (SIC), a total SI suppression of >60 dB is achieved over a 2-GHz bandwidth. The proposed neutralized mixer with over 20-dB LO feedthrough suppression and wideband RF amplifiers support a large data rate at sub-THz frequencies. This is the world’s first demonstrated sub-THz FD phased-array TRX. In the over-the-air (OTA) measurements for FD mode, the proposed FD TRX achieves 6 Gb/s in 8PSK and 4 Gb/s in 16QAM. It also achieves a 112-Gb/s data rate for OTA TX-to-RX.

This article presents a low-power 256-element $Ka$ -band CMOS phased-array receiver utilizing ON-chip distributed radiation sensors for the low Earth orbit (LEO) small satellite communication system. Since the available solar cell area limits the power generation of the small LEO satellites, a distributed current-sharing common-gate (CG) low noise amplifier (LNA) and a voltage-tuning variable gain amplifier (VGA) are introduced to reduce power consumption. After utilizing the proposed technique, the power consumption of the beamformer is 2.95 mW/element. Moreover, the proposed voltage-tuning VGA is configured to utilize both upper and lower transistors for gain contributions to save power. The ON-chip distributed radiation sensors are presented to eliminate the non-uniform radiation influence and realize 0.22-dB/Mrad gain degradation performance. The proposed receiver achieves −20-dBm single-element IIP3 with a 3.6-dB noise figure. The occupied ON-chip area for a single element is only 0.24 mm2. DVB-S2X standard modulated signals of up to 256 amplitude and phase-shift keying (APSK) can be supported in the over-the-air (OTA) measurement. The receiver achieves −31.3-dB EVM and 24-Gb/s link speed under 1.5-GBaud dual-linear polarization signals. The measured 256-element beam pattern can cover radiated angle from −50° to +50° with lower than −9-dBc sidelobe level. Thanks to the proposed low-power distributed current-sharing CG LNA and ON-chip radiation sensors, a low-power radiation-hardened phased-array receiver can be achieved for the small LEO satellites.

This article introduces a high-accuracy phase and amplitude detection circuit for 5G phased-array calibration. By utilizing a 39 GHz–150 kHz down-conversion scheme, the phase and amplitude information are detected separately with a phase-to-digital converter (PDC) and an analog-to-digital converter (ADC). In addition, to reduce the number of reference signals, a divide-by-4 injection-locked frequency divider (ILFD) using a transformer-based injection-enhancing technique is implemented for wideband reference signal generation. This ILFD realizes a wide locking range of 16.3–23.4 GHz (35.8%) with 5.05-mW power consumption. The detection circuit achieves less than 0.049° and 0.036-dB detection rms errors at 39 GHz. The wideband high-accuracy detection is also achieved from 37 to 43.5 GHz. The total power consumption is 50 mW with a 1-V VDD. The total core area is 1.43 $\text {mm}^{2}$ in a 65-nm CMOS process.

This article demonstrates a 39-GHz CMOS phased-array beamformer aiming for power-efficient and area-efficient fifth-generation (5G) dual-polarized multiple-in–multiple-out (DP-MIMO) applications. To address the digital pre-distortion (DPD) implementation issue in the massive beamformer elements with Doherty technique integrated, an inter-element mismatch compensation technique is introduced for improving the shared-lookup table (LUT) DPD performance over the process, voltage and temperature (PVT) variations. A bidirectional Doherty power amplifier (PA)-LNA is proposed to enhance the power back-off (PBO) efficiency regarding the high peak-to-average power ratio (PAPR) 5G signals, meanwhile cost down the system by the unbalanced neutralized bidirectional operation. The proposed phased-array beamformer chip is fabricated in 65-nm CMOS technology and packaged in a wafer-level chip-scale package (WLCSP). Each element occupies only a 0.82-mm2 chip area, including the on-chip low-dropout regulator (LDO). The measured stand-alone Doherty PA-LNA achieves 18.9-dBm saturated output power with 17.8% power-added efficiency (PAE) at 6-dB PBO in PA mode and obtains a 4.8-dB noise figure (NF) at 40 GHz in LNA mode. By utilizing the proposed mismatch compensation, the measured 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiple access (OFDMA)-mode error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) with the shared-LUT DPD are improved from −22.4 to −25.0 dB and from −28.7 to −32.1 dBc, respectively. The 64-element module achieves a 55.2-dBm saturated effective isotropic radiated power (EIRP) and supports 21-Gb/s single-carrier (SC) mode data streaming. The measured 64-element transmitter (TX) EVM is −25.2 dB at 43.2 dBm with 3.5-GSymbol/s baud rate in 64 QAM, and the corresponding 64-to-4 elements TX-to-receiver (RX) EVM is −22.5 dB. The consumed power for each element is 402 mW at saturation output point in TX mode and 87 mW in RX mode.

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional- ${N}$ multiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional- ${N}$ and integer- ${N}$ modes, respectively. The fractional spur is less than −59.0dBc, and the reference spur is −64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of −240.4dB and −245.5dB. [ABSTRACT FROM AUTHOR]

This article presents a small-area Bluetooth Low-Energy (BLE) transceiver (TRX) for short-range Internet-of-Things (IoT) applications in 65-nm CMOS. An integrated Radio-Frequency Input-Output (RFIO) circuitry embedded with transmitter/receiver (TX/RX) switch function and on-chip impedance matching is proposed. A hybrid-loop TRX structure based on a wide-bandwidth fractional-N digital phase-locked loop (DPLL) is implemented to achieve the maximum power reduction. A −94dBm receiver sensitivity is achieved with 2.3mW receiver power consumption, while a RF receiving bypass route integration enhances the input power tolerance. The BLE transceiver delivers −6dBm output power while consuming 2.6mW and delivers 0dBm output power while achieving 18.5% maximum TX efficiency. Thanks to the RFIO with harmonic suppression, −56dBc of 2 $^{\mathrm{ nd}}$ -order harmonic distortion (HD2) and −48dBc of 3 $^{\mathrm{ rd}}$ -order harmonic distortion (HD3) suppression are achieved with 0.85mm2 on-chip area. This transceiver satisfied the BLE radio specification without the need for external filters and with low-power consumption, which enables minimum size and long life-time modules. [ABSTRACT FROM AUTHOR]

A planar solenoidal inductor for the realization of a variable inductor with a wide tunable range and a high quality factor (Q-factor) is proposed in this work. Prototype inductors are designed and fabricated using a two-metal micro-electro-mechanical systems (MEMS) process to demonstrate the potential use of the tunability of the inductance and the Q-factor. Inductance tuning from 1 to 3.3 nH was achieved and the tunability obtained was as high as 230% at 2 GHz. A Q-factor of more than 20 was observed in the frequency range of 2.5 to 6 GHz.

This work proposes a micro electro mechanical systems (MEMS)-based digitally controlled solenoid-inductor. The inductor is fabricated by using a MEMS process. 2-bit tuning characteristics are measured, and tuning linearity and $Q$-factor degradation due to switching loss are discussed. The linear inductance tuning from 1.7 to 2.2 nH was achieved at 2 GHz. A $Q$-factor of more than ten was observed in the frequency range of 1.2 to 7.4 GHz. The validity of the proposed inductor was confirmed by investigating the effect of switch resistance.