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Falls can be one of the most damaging events that elders may experience in their lives, especially when they live alone. The impact of a fall can vary from minor bruises, to life altering fractures and even become fatal. The purpose of this study is to establish a novel non-contact radar method of detecting an elderly fall when occurred in home staying. The novelty of the proposed detection technique is the exploitation of a 1D effective acceleration derived from Short Time Fourier Transform (STFT). This technique was tested utilizing a 2.45 GHz Continuous Wave (CW) Radar implemented with a Software Defined Radio (SDR) and low-cost, off-the-shelf components. Herein, we present test results that classify incidents as either falls or non-falls in line-of-sight cases. Firstly, the results are compared with the corresponding values measured with a commercial marker-based optoelectronic motion capture multi-camera system (VICON) showing high similarity. Furthermore, real-time scenarios were conducted to estimate the accuracy and the number of false alarms of the proposed method. The proposed algorithm is proved capable of exploiting the Power Burst Curve (PBC) as a preliminary factor to yield an efficient fall incident classifier based on the effective acceleration, while minimizing the required processing resources.

Aim: The present study aimed to assess the sensitivity, specificity and construct validity of the General Practice Physical Activity Questionnaire (GPPAQ) and two modified versions, GPPAQ-WALK and GPPAQ-WALK-Old in retired, community-dwelling older adults, 60–90 years. Methods: Participants completed assessments from the Senior Fitness Test (lower limb strength, dynamic balance, aerobic endurance) and used a waist-worn accelerometer for a week, following which they responded to the GPPAQ. Active/non-active GPPAQ classification was compared against accelerometry regarding meeting/not meeting the guidelines of ≥ 150 min/week of moderate-to-vigorous physical activity (MVPA). Sensitivity and specificity were calculated. T tests compared BMI and fitness scores between active and non-active participants. Results: A total of 180 retired adults residing in Greece, mean age 72.82 ± 6.30, participated in the study, 114 of whom had valid accelerometer data corresponding to the GPPAQ recall week. The GPPAQ active classification showed 4.4% sensitivity and 97.4% specificity but did not differentiate active and non-active participants regarding BMI and physical fitness. The GPPAQ-WALK showed 27.8% sensitivity and 80.8% specificity, with active participants performing better in dynamic balance and lower limb strength than non-active. The GPPAQ-WALK-Old showed 69.4% sensitivity and 44.9% specificity. Active participants had lower BMI, better lower limb strength and dynamic balance than non-active. Conclusion: With an interest in increasing awareness of the importance of PA and improving public health outcomes through PA promotion in insufficiently active older adults, we advocate that the GPPAQ-WALK can be a useful tool in healthcare and other community settings. Further modifications to fully assess adherence to PA guidelines for older adults are proposed.

In recent years, the intrinsic neuromorphic properties of memristor devices have led to their extensive use in brain-inspired circuits and systems. The development of brain-inspired (nano)circuits incorporating memristors has the potential to revolutionize the field of neuromorphic engineering. This brief presents a novel circuit design of Basal Ganglia (BG), with the Memristor-Based Oscillator (MBO), which takes a significant step forward in this direction. The MBO circuit utilizes low-power fitted Conductive-Bridging RAM (CBRAM) devices with distinct neuromorphic features, making it a promising tool for both research and treatment of neurodegenerative diseases such as Parkinson’s Disease (PD). Additionally, the circuit incorporates modeled synapses exhibiting both excitatory and inhibitory behavior and is calibrated to match the performance of fabricated devices. The MBO circuit is well-suited for incorporation in brain-inspired networks and can accurately replicate neuronal behavior, resulting to a low-cost emulator for PD and other neurodegenerative diseases compared with other hardware approaches. In this brief, the Parkinsonian Network (PN) was replicated and then the Deep Brain Stimulation (DBS) methodology was applied, showing promising results for the development of memristor-based brain-inspired nanocircuits.

A novel miniature all-polarization $\Gamma $ antenna array for demanding 5G and the Internet of Things (IoT) applications is proposed. The antenna is designed to be able to perform direction of arrival (DoA) and beamforming keeping the antenna’s footprint as minimal as possible to fit in or wrapped around any IoT device. It is a nonuniform square array comprised of novel right-corner dipoles which are mirror-placed to additionally allow all polarization properties. These properties are inherited from its approximate equivalence to a cross-dipole antenna with additional features and flexibility. An analytical mathematical formulation is presented resulting in a closed form for the $\Gamma $ –dipole as well as the four dipoles array. Numerical simulations proved the antenna performance and verified that all of its features are approximately retained even when it is curved. The antenna is prototyped in both an improvised wire dipole (planar or curved) and as printed on an FR-4 substrate. The measured results confirmed the analytical and numerical ones regarding the antenna all-polarization, beamforming, and DoA features.

Approximate computation has evolved recently as a viable alternative for maximizing energy efficiency. One aspect of approximate computing involves the design of hardware units that return a sufficiently accurate result for the examined occasion, rather than computing an accurate result. As long as the hardware units are allowed to compute approximately, they can be designed with multiple new ways. In this work, we focus on the synthesis of approximate parallel-prefix adders. Instead of exploring specific architectures, as done by state-of-the-art approaches, the introduced synthesizer can produce every solution that meets the designer’s criteria, resulting in adders with various delay, area, and error tradeoffs. This automatic design space exploration allows approaching, in several cases, optimal solutions that could have not been designed with any other known parallel-prefix architecture. The synthesized adders, when compared with state-of-the-art adders, achieve 27%–36% better error frequency (EF) on average for random inputs and improve image quality metrics by 8%–42% for image filtering. These results are achieved with the proposed adders requiring the same or marginally more hardware area or energy. On the contrary, in split-accuracy configurations, more than 30% of hardware area/energy can be saved for the same classification accuracy for a neural network application.

This Special Issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is devoted to showcase the latest research achievements on memristive circuits and systems with special focus on edge-computing applications. Over the past few years, the field of circuits and systems has witnessed significant changes, which have inevitably accompanied the progressive approach of the CMOS technology aggressive downscaling trend to an unavoidable end, given the clear impossibility to reduce the transistor dimensions below the atomic scale, in the near future. Tremendous efforts are being made in search for novel devices and circuits toward the development of disruptive nanotechnologies, enabling the fabrication of multi-purpose devices and circuits, which would allow to foster sustainable progress in integrated circuit design, despite further shrinking in transistor sizes shall no longer be feasible soon. In this regard, memristors, exhibiting the extraordinary capability to combine, within a single miniaturized 3-D space, data sensing, processing, and storage functionalities, offer a plethora of novel opportunities for integrated circuit design, paving the way toward the conception of multi-purpose CMOS-compatible nano-circuits, which are bound to improve the performance of state-of-theart computing machines.

Computing demands are growing rapidly as bigdata and artificial intelligence applications become increasingly tasking. Bio-inspired and quantum-based techniques are proving to be quite promising for the development of novel circuits and systems. These systems can contribute to the resolution of a wider variety of problems while also providing improvements to existing techniques. As the von Neumann architecture’s expected performance, which has been dominant for the past several decades, is now hindered by physical limitations, novel computing architectures, assisted by novel materials and circuit devices, are starting to emerge and provide promising results. The topic of this work is to examine the memory and computing capabilities of emergent memristor-based nanocircuits and demonstrate their advantages compared to their classical counterparts.

One of the most enticing candidates for next-generation computing systems is the memristor. Memristor-based novel architectures have demonstrated considerable promise in replacing or augmenting traditional computing platforms based on the Von Neumann architecture, which faces many issues in the big-data era, as well as in newly developed neuromorphic tasks. Although the current classical computing architecture is unlikely to be abandoned in the foreseeable future, the growing trend of neuromorphic, quantum, and bio-inspired computing schemes calls for more specialized beyond Von Neumann platforms. Memristors showcase multiple advantages in terms of small area footprint, energy efficiency, high endurance, bio-compatibility, and their inherent synaptic and neuromorphic behavior. The topic of this work is to present the memristive devices that meet the requirements for the implementation of the novel beyond Von Neumann applications and examine their switching mechanism and material selection, as well as to conduct a performance comparison between the fabricated devices paving the way for future computing applications.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Synchronization transition in neuromorphic networks has attracted much attention recently as a fundamental property of biological neural networks, which relies on network connectivity along with different synaptic features. In this work, an area-optimized FPGA implementation of an Asynchronous Cellular Automata Neuron model that exhibits discrete-state neuron dynamics is introduced. The proposed neuron model is capable of reproducing various neuromorphic oscillations observed in biological neurons using less hardware resources than previous implementations. We investigate synchronization transitions with a focus on the emergence of chimera states in a ring-based network consisting of hardware-based neurons with electrical synaptic coupling. In particular, we study the effects on the network’s phase synchronization through changing two control parameters: the coupling range and the coupling strength. We indicate that via proper configuration of the coupling parameters, we influence the synchronization transition and reveal chimera states which have been associated with neurological disorders. [ABSTRACT FROM AUTHOR]

There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today’s classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm. [ABSTRACT FROM AUTHOR]

Electrostatically doped graphene p–n junctions can modulate graphene nanoribbon conductance and can be indispensable parts of nanoelectronic graphene circuits. Much research has been conducted on such devices with one rectangular top gate and one back gate with very encouraging results. Recently, graphene p–n junctions with two rectangular top gates have been proposed and their study revealed a rich behaviour that allows their use in both analogue and digital nanoelectronic circuits. Here we study graphene p–n junctions with two trapezoid top gates and a common back gate with special focus to the effect of the angle and the distance between the two top gates. Furthermore, trapezoid top gates with angles of 45° make use of the Veselago lens effect, allowing an effective control by tuning density of states and carrier density. We simulated these devises using the non-equilibrium Green’s function method combined with tight-binding Hamiltonians in the ballistic transport limit. Our results show that the conductance of these graphene p–n junctions can be successfully controlled by various combinations of different parameters that allows for realisation of carbon-based logic gates. We also present the design and simulation a universal set Boolean gates, namely NOT, NAND and NOR.

This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

Nonlinear circuits may be synchronized with interconnections that evolve in time incorporating mechanisms of adaptation found in many biological systems. Such dynamics in the links is efficiently implemented in electronic devices by using memristors. However, the approach requires a massive amount of interconnections (of the order of N^2 , where $N$ is the number of nonlinear circuits to be synchronized). This issue is solved in this paper by adopting a memristor crossbar architecture for adaptive synchronization. The functionality of the structure is demonstrated, with respect to different switching characteristics, via a simulation-based evaluation using a behavioral threshold-type model of voltage-controlled bipolar memristor. In addition, we show that the architecture is robust to device variability and faults: quite surprisingly, when faults are localized, the performance of the approach may also improve as adaptation becomes more significant. [ABSTRACT FROM PUBLISHER]

The ability of slime mould to learn and adapt to periodic changes in its environment inspired scientists to develop behavioral memristor-based circuit models of its memory organization. The computing abilities of slime mould Physarum polycephalum have been used in several applications, including to solve mazes. This work presents a circuit-level bio-inspired maze-solving approach via an electronic model of the oscillatory internal motion mechanism of slime mould, which emulates the local signal propagation and the expansion of its vascular network. Our implementation takes into account the inherent noise existent in the equivalent biological circuit, so that its behavior becomes closer to the non-deterministic behavior of the real organism. The efficiency and generality of the proposed electronic computing medium was validated through SPICE-level circuit simulations and compared with data from two cardinally different biological experiments, concerning 1) enhancing of Physarum's protoplasmic tubes along shortest path and 2) chemo-tactic growth by diffusing chemo-attractants. [ABSTRACT FROM AUTHOR]

Aircraft are profitable to their owners as long as they are in the air transporting passengers to their destinations; therefore it is vital to minimize as much as possible their preparation time on the ground. In this paper we simulate different boarding strategies with the help of a model based on cellular automata parallel computational tool, attempting to find the most efficient way to deliver each passenger to her or his assigned seat. Two seat arrangements are used, a small one based on Airbus A320 U+002F Boeing 737 and a larger one based on Airbus A380 U+002F Boeing 777-300. A wide variety of parameters, including time delay for luggage storing, the frequency by which the passengers enter the plane, different walking speeds of passengers depending on sex, age and height, and the possibility of walking past their seat, are simulated in order to achieve realistic results, as well as monitor their effects on boarding time. The simulation results indicate that the boarding time can be significantly reduced by the simple grouping and prioritizing of passengers. In accordance with previous papers and the examined strategies, the outside-in and reverse pyramid boarding methods outperform all the others for both the small and large airplane seat layout. In the latter, the examined strategies are introduced for first time in an analogous way to the initial small seat arrangement of Airbus A320 U+002F Boeing 737 aircraft family. Moreover, since in real world scenarios, the compliance of all the passengers to the suggested group division and boarding strategy cannot be guaranteed, further simulations were conducted. It is clear that as the number of passengers disregarding the priority of the boarding groups increases, the time needed for the boarding to complete tends towards that of the random boarding strategy, thus minimizing the possible advantages gained by the proposed boarding strategies.

The history of computing is inextricably bounded and heavily dependent on materials technology advances, especially nanotechnology. During the last decade, we have witnessed significant nanotechnology science discoveries from memristive and spin-orbit torque materials, carbon nanotubes to graphene, and biomaterials that have enabled several novel computing ways usually entitled under the generic term of unconventional computing. A common characteristic of these unconventional computing paradigms is their intrinsic capability to outperform, in terms of specific figures of merit, traditional von Neumann related computing architectures.

Nowadays, the huge power consumption and the inability of the conventional circuits to deal with real-time classification tasks have necessitated the devising of new electronic devices with inherent neuromorphic functionalities. Resistive switching memories arise as an ideal candidate due to their low footprint and small leakage current dissipation, while their intrinsic randomness is smoothly leveraged for implementing neuromorphic functionalities. In this review, valence change memories or conductive bridge memories for emulating neuromorphic characteristics are demonstrated. Moreover, the impact of the device structure and the incorporation of Pt nanoparticles is thoroughly investigated. Interestingly, our devices possess the ability to emulate various artificial synaptic functionalities, including paired-pulsed facilitation and paired-pulse depression, long-term plasticity and four different types of spike-dependent plasticity. Our approach provides valuable insights from a material design point of view towards the development of multifunctional synaptic elements that operate with low power consumption and exhibit biological-like behavior.

Due to its unexpected computing abilities, Physarum polycephalum, a vegetative stage of acellular slime, has been repeatedly used during the last decade in order to reproduce transport networks. After conducting a series of biological experiments and with the help of a Cellular Automata (CA) model we try to explore the ability of the slime in order to imitate the Roman road network in the Balkans, an area which was of great strategic importance for the stability of the Roman Empire in the East. The application of Physarummachines hopes to offer a first step towards a new interdisciplinary, almost unconventional, approach to archaeology.

The existence of the fourth fundamental circuit element, the memristor, was first postulated over 30 years ago by Leon Chua. The implementation of the first modern memristor prototype by Hewlett Packard Laboratories in 2008 initiated a great scientific interest for these unique nanoelectronic devices and currently, there is a growing variety of systems that exhibit memristive behavior. However, most of the research has focused on the properties of the single devices, therefore very little is known about their response when these devices are organized into networks. In this work, the composite characteristics of memristive elements connected in network configurations are studied and the relationships among the single devices are investigated. We finally show how the threshold-dependent nonlinear memristive behavior could be elaborated to make possible the development of novel and sophisticated digital/analog memristive nanosystems.

Resistance switching devices are of special importance because of their application in resistive memories (RRAM) which are promising candidates for replacing current nonvolatile memories and realize storage class memories. These devices exhibit usually memristive properties with many discrete resistance levels and implement artificial synapses. The last years, researchers have demonstrated memristive chips as accelerators in computing, following new in-memory and neuromorphic computational approaches. Many different metal oxides have been used as resistance switching materials in MIM or MIS structures. Understanding of the mechanism and the dynamics of resistance switching is very critical for the modeling and use of memristors in different applications. Here, we demonstrate the bipolar resistance switching of silicon nitride thin films using heavily doped Si and Cu as bottom and top-electrodes, respectively. Analysis of the current-voltage characteristics reveal that under space-charge limited conditions and appropriate current compliance setting, multi-level resistance operation can be achieved. Furthermore, a flexible tuning protocol for multi-level resistance switching was developed applying appropriate SET/RESET pulse sequences. Retention and random telegraph noise measurements performed at different resistance levels. The present results reveal the attractive properties of the examined devices. [ABSTRACT FROM AUTHOR]

Memristors have been utilized as an unconventional computational substrate and gained interest as a medium to implement neuromorphic computations. A mathematical model that also proved its potential is Learning Cellular Automata, that is an amalgam of Cellular Automata and Learning Automata. The realization of the common characteristics of memristive circuits and Learning Cellular Automata can only lead to their combination. Namely, both manage to blend storage and processing capabilities in their basic entity. This study involves the definition of memristive circuits that realize the computing behavior of Learning Cellular Automata. An example of this methodology is provided with the description of the implementation of edge detection for image processing. [ABSTRACT FROM AUTHOR]