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This paper presents two novel automated transistor width optimisation algorithms based on Levenberg-Marquardt (LM) algorithm (embedded in SPICE) and logical effort theory proposed by Sutherland et al. (2004). This paper has incorporated the complete logical effort theory from scratch in TCL; hence, it works independent of SPICE tool and can optimise any number of transistors present in circuit. The algorithm can be used as open source optimisation tool and modifications can be done to it according to the need. The proposed algorithms can be utilised for automated library cell characterisation where precise and large numbers of driving strength cells are required. Since the algorithms are automation based, they can play a pivotal role in development of library less synthesis. Optimisations results using proposed algorithms were obtained for both sequential logic blocks (flip-flop) and combinational logic blocks (basic logic gates). Both the algorithms have their own advantages and disadvantages.

This paper presents a comprehensive comparison between Levenberg-Marquardt (LM) and logical effort (LE) theory-based optimisation techniques. While LM is a classical approach for optimisation and is embedded in SPICE, logical effort-based approach is contemporary, design specific and needs simple back of the envelope calculations for optimisation of digital circuits. Both the approaches have been used by digital circuit designers in the literature for comparing a proposed digital circuit with the existing designs while optimising any given design for timing, power and area parameters. The goal of writing this paper is to make digital system designers gain an insight into the procedures used for optimising digital circuits while at the same time a well-defined approach using LM algorithm is provided that can be easily automated with the current generation CAD tools. For the purpose of comparison some standard circuits were chosen and optimised for minimum PDP and PDAP. SPICE simulations have been extensively used for comparing the two methodologies in a 180 nm\1.8 V CMOS technology.