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The radiation hardness of 4H-SiC MOSFETs with LOCal Oxidation of SiC (LOCOSiC) isolation structures is evaluated in this work. NMOSFETs and PMOSFETs utilizing a 40-nm-thick thin oxide and a 200-nm-thick Field Oxide (FOX) as the gate oxide were fabricated and subsequently exposed to gamma-ray irradiation. In comparison to conventional Chemical Vapor Deposited (CVD) FOX, the LOCOSiC-isolated thin oxide MOSFETs exhibit a similar degree and trend of degradation after gamma-ray exposure. Regarding the FOX MOSFET, the positively trapped oxide charge in the FOX generated by irradiation leads to a decrease in the threshold voltage of the CVD FOX MOSFET. Conversely, the defect layer beneath the LOCOSiC FOX pins the surface potential, enabling the LOCOSiC FOX MOSFET to remain in the turn-off state even when the irradiation dose reaches 100 kGy and the gate bias increases to 24 V. These findings suggest that LOCOSiC isolation possesses exceptional radiation hardness and holds potential for application in SiC devices operating in strong radiation environments.

In this study, metal contact on p-type SiC with low specific contact resistance was developed using TiAl. Using fine-tuned TiAl deposition and annealing conditions on p-type SiC, the Ti–Si–C interfacial layer grown on high temperature ion implanted $\text{P}^{+}$ SiC is nonuniform and exhibits nonohmic behavior when the contact area becomes smaller than $10\,\,\mu \text{m}\,\,\times 10\,\,\mu \text{m}$ . This area dependence can be improved through low-energy, room-temperature (LERT) ion implantation and Ar plasma treatment prior to metal deposition. Ar plasma treatment results in a uniform Al–Si–C interfacial layer. Moreover, the defects produced by LERT ion implantation promote trap-assisted tunneling. Through the aforementioned methods, metal contact on p-type SiC with a record-low specific contact resistance of $3\times 10^{-{5}}\,\,\Omega $ cm2 at record-small contact area of $1.5\,\,\mu \text{m}\,\,\times 1.5\,\,\mu \text{m}$ was obtained in this study.

4H-SiC complementary metal-oxide-semiconductor (CMOS) devices for control circuit applications have been reported extensively, however, the electrical stability, even with interface optimization processes, degrades significantly after bias stress. In this paper, we performed both positive and negative bias stress on planar SiC NMOSFETs and PMOSFETs fabricated with pure (non-diluted) and N2-diluted NO post-oxidation annealing (POA) processes. The test results indicate the existence of positive hole traps might be the culprit that leads to electrical characteristics instability during operation and pure NO annealing is effective to reduce the instability.

The effect of post-ion implantation annealing on the properties of the SiO2/4H-SiC interface is examined in this paper. It is observed that the surface roughness degrades after the high-temperature Ar annealing, but the oxidation process after the high temperature annealing can improve the surface roughness. To better understand the effect of high-temperature annealing on the gate oxide, the reliability of gate oxide is further studied. The results show that although the surface roughness degrades after high-temperature annealing, the interface state density, tunneling barrier height, breakdown field, and critical electric field for the 10-year lifetime of the thermally grown gate oxide do not degrade.

In this article, the narrow-width effect (NWE) of 4H-SiC MOSFETs with local oxidation of SiC (LOCOSiC) isolation is reported. A channel width-dependent current hump was observed in the subthreshold region for n-type 4H-SiC MOSFETs with LOCOSiC, and a channel width-dependent threshold voltage ( ${V} _{th}$ ) shift was observed for p-type 4H-SiC MOSFETs with LOCOSiC. This unusual NWE arises from the increase in the gate oxide thickness from the channel center toward the isolation edge and is different from the conventional NWE found in local oxidation of silicon (LOCOS) technology, which arises from the charge stored in the parasitic field oxide (FOX) capacitor and lateral dopant encroachment. A H2O diffusion and oxidation model is proposed in this article to explain the growth of a long bird’s beak in 4H-SiC MOSFETs with LOCOSiC. Technology computer-aided design (TCAD) simulations were executed to explore the H2O diffusion behavior of these MOSFETs, and an analytical formula was derived to predict the oxide layer thickness and length of bird’s beak along the diffusion path in the H2O diffusion and oxidation model. The problems caused by the long bird’s beak and unusual NWE can be overcome by increasing the overetching time of the pad oxide removal and marginally decreasing the thickness of the FOX layer. Therefore, the NWE of the LOCOSiC isolation is expected to be weaker than that of the LOCOS isolation because field implantation is unnecessary, and thus, dopant encroachment does not occur in the LOCOSiC technology.

In this study, the performance of complementary metal–oxide–semiconductor (MOS) circuits fabricated on SiC substrates was investigated by designing several digital and analog circuits, and a unique process flow was developed to integrate n-type MOS (NMOS) and p-type MOS (PMOS) transistors with low and high threshold voltages (Vth) into a single chip. A detailed process flow with local oxidation of SiC isolation and a dual gate oxide with a compromised gate dielectric are presented. The performance of NMOS field-effect transistors (FETs) and PMOSFETs with low and high Vthwere characterized in detail. Lateral MOS capacitors were also fabricated in the same chip to explore the characteristics of the gate dielectric. Several common logic gate components were fabricated and tested at elevated temperatures to demonstrate the normal function of these elements in a digital circuit. Static random-access memory (SRAM) cells were designed and optimized through simulation. Characterizations of all the circuit blocks are presented to demonstrate the capability of these circuits in harsh environments.

In this work, we investigated the impact of carbon ion implantation on the thermal stability of nickel silicide film and nickel-silicide-contact n+/p shallow junctions. A higher carbon ion implantation dose can prevent the nickel silicide film from agglomeration and phase transformation. However, good thermal stability does not necessarily lead to excellent junction current--voltage characteristics owing to the diffusion of nickel atoms. When the carbon ion implantation dose increases to $5\times 10^{15}$ cm-2, many crystal defects are created. Then, numerous nickel atoms diffuse along these defects into the junction depletion region during the silicide formation process, resulting in poor junction characteristics. The trade-off between thermal stability and junction electrical characteristics is discussed in this paper. Finally, two methods are suggested to solve the serious leakage current problem.

The thermal stability of nickel monosilicide (NiSi) is one of the important research topics in the area of nano-complementary metal oxide semiconductor. This paper reports the effect of germanium (Ge) ion implantation on the thermal stability of the NiSi∕Sistructure. High dose Ge ion implantation (5×1015cm−2)can improve the thermal stability of the NiSi∕Sistructure. Ge ion implantation before NiSi formation results in a very smooth NiSi∕Siinterface due to Ge atom pileup at the NiSi∕Siinterface. This high concentration Ge layer reduces the interface energy so that the thermal stability can be improved. Both the phase-transformation temperature and agglomeration temperature are improved by 50–100°C. The effects of Ge ion implantation on the NiSi-contacted n+-pand p+-nshallow junctions are also examined. Although fast Ni diffusion via the ion implantation induced defects is observed, better thermal stability can still be observed on the n+-pjunction.

The thermal stability of nickel silicide (NiSi) on source/drain and gate is one of the important research topics in complementary metal oxide semiconductor technology. Here we report the effects of germanium-ion implantation (GeI∕I)on the thermal stability of NiSi on poly-Si gates. Scanning electron microscope inspections and thin-film X-ray diffraction results show that agglomeration and NiSi2transformation can be suppressed by high dosage Ge implanted on poly-Si gates. The allowable process temperature of NiSi formation can be increased by 100°C.

In this work, high-performance TiN metal nanocrystal nonvolatile memories using a p+poly-Si gate and a Al2O3blocking dielectric layer with trigate structure are fabricated on silicon-on-insulator substrate. Devices with moderate transistor performance and superior memory properties are demonstrated. A memory window as high as 5Vis achieved after Program/Ease (P/E) operation at ±10Vfor 0.1s, with only 18 and 33% charge loss at room temperature and at 85°Cafter 10yearsstorage. Only +0.5Vwindow shift and almost no window narrowing after 105P/E operations can be obtained. Furthermore, a device with larger nanocrystals has better P/E characteristics and superior retention performance.