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This paper proposes ElevatorTalk, an elevator development and management system based on the Internet of Things (IoT) approach called IoTtalk. This system modularizes the software into elevator components so that we can develop flexible and scalable car scheduling algorithms. ElevatorTalk consists of three subsystems: cars, scheduler, and the elevator car operating (ECO) panel. The first two subsystems are used to develop the elevator systems, and the third subsystem is used to receive requests issued by the passengers. These three subsystems work in parallel, and communicate with each other through sending and receiving messages. ElevatorTalk can connect to a real elevator system to serve as the elevator management center. It can also emulate the existing elevator systems with different car scheduling algorithms. We propose an intelligent aggressive car scheduling with initial car distribution (ACSICD) algorithm in ElevatorTalk. Our paper indicates that ACSICD has better waiting/travel/journey time performance and/or accuracy than the previous proposed algorithms. We also show that in our approach, the car scheduling decision can be quickly made with 0.2010 ms, and therefore good performance in the time complexity is achieved.

We propose a progressive radiance estimation engine (PREE) hardware architecture to accelerate the processing of the progressive photon mapping with satisfactory graphic quality. The presented PREE architecture consists of four progressive radiance estimation units (PREUs), approximate full task schedule-oriented hit-point update operation controller (AFTSO-HpUOC) and approximate data-independent schedule-oriented radiance evaluation controller (ADISO-REC). The PREUs accelerate the radiance estimation computation by a pipeline technique and share and configure the hardware resource for hit-point update operation and radiance evaluation. Through AFTSO-HpUOC and ADISO-REC, the data can be efficiently dispatched to achieve better parallelism and the data dependence can be alleviated within the four PREUs, respectively. The core area of the proposed PREE architecture implemented in TSMC 90-nm CMOS process is 1.78 mm2. According to the post-layout simulation results, the implementation achieves 496.79 million hit-point update operations per second (MHpUO/s) and consumes 184 mW at 125 MHz for Cornell box with three balls. [ABSTRACT FROM AUTHOR]

In this paper, a power-area efficient geometry engine (GE) using a low-complexity three-level subdivision algorithm is presented. The proposed subdivision algorithm and architecture is capable of providing low complexity, high power-area efficiency, scalable and near-Phong shading quality. The forward difference, edge function recovery, dual space subdivision, triangle filtering, and triangle setup coefficient sharing schemes are employed to alleviate the redundant computation for the proposed algorithm. According to the low-complexity subdivision algorithm, one reconfigurable datapath is proposed to save the area since the same set of processing elements (PE) is reused for different operations of GE. Compared with the conventional subdivision algorithm, the proposed subdivision algorithm reduces the number of memory/register accesses for subdivision by 40% and 60.32% for level-1 and level-2 subdivision, respectively. In terms of the number of multiplications for transforms, the reduction can be attained by 27.5% and 60.27% for level-1 and level-2 subdivision, respectively. From the implementation results, the proposed GE can achieve the power-area efficiency of 518.8 Kvertices/(s\bulletmW\bulletmm^2) for level-1 subdivision. [ABSTRACT FROM PUBLISHER]

This paper presents two-dimensional (2-D) VLSI digital filter structures possessing various symmetries in the filter magnitude response. For this purpose, four Type-1 and four Type-2 power-efficient and cost-effective 2-D magnitude symmetry filter architectures possessing diagonal, fourfold rotational, quadrantal, and octagonal symmetries with reduced number of multipliers and one power-efficient and cost-effective multimode 2-D symmetry filter are given. By combining the identities of the four Type-1 symmetry filter structures, the proposed multimode 2-D symmetry filter is capable of providing four different operation modes: diagonal symmetry mode (DSM), fourfold rotational symmetry mode (FRSM), quadrantal symmetry mode (QSM), and octagonal symmetry mode (OSM). The proposed diagonal, fourfold rotational, quadrantal, and octagonal symmetry filter structures can attain power savings of 16.77%, 36.30%, 22.90%, and 37.73% with respect to that of the conventional 2-D filter design without symmetry. On the other hand, the proposed DSM, FRSM, QSM, and OSM modes can reduce power consumption by 11.01%, 31.42%, 17.53%, and 35.26% compared with that of the conventional 2-D filter design. The proposed multimode filter can result in a 63.25% area reduction compared with the sum of the areas of the four individual Type-1 symmetry filter structures. [ABSTRACT FROM PUBLISHER]