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This article presents an energy-efficient microprocessor design that fully integrates an error-resilient RISC-V core and an embedded dc–dc switched-capacitor voltage regulator (SCVR). The proposed design achieves high energy efficiency, high computation performance, and a small system footprint through several innovations. First, in situ error detection and correction (EDAC) flip-flops (FFs) and an error-resilient static random access memory (SRAM) interfacing technique enable error resilience on the microprocessor without any post-silicon calibration requirement. Next, a fully integrated SCVR featuring a multi-rate successive approximation (MRSA) algorithm and a dynamic conduction loss minimization technique is proposed to achieve high conversion efficiency, high-power density, and fast load regulation. A prototype chip that fully integrates the techniques described above was fabricated in the 28-nm standard CMOS technology with an active area of 0.42 mm2. The measurement results show that the proposed in situ EDAC effectively minimizes the timing margin without any post-silicon calibration to achieve a high-processor performance of 43 MHz with an energy-delay-product (EDP) of 0.57 $\text {pJ}\cdot \mu \text{s}$ , showing the state-of-the-art performance and energy efficiency in the standard CMOS technology.

This paper presents a 28-nm 32kb 6T static random access memory (SRAM) operating down to the sub-threshold regime. This design employs a dual-phase VDD (DPVDD) control technique in a row-based manner to reduce the minimum functional voltage (Vmin) below the threshold voltage of the transistor (Vth). With the proposed DPVDD technique, during the read operation, the ratio of the read current to the leakage current caused by the unselected bit-cells on the same bit-line is increased by a temporally boosted cell VDD, which increases the signal swing on the bit-line and minimizes the stability degradation caused by the leakage current. In addition, the proposed DPVDD can enhance the stability of the half-selected cells to mitigate the half-select disturbance. A 32-kb 6T SRAM test chip was implemented in 28-nm CMOS technology with a macro area of 0.028 mm2. Measurement results show that the SRAM with the proposed DPVDD achieves Vmin of 0.27 V and the minimum energy of 0.041 fJ/bit. [ABSTRACT FROM AUTHOR]

The output ripple of switched-capacitor dc–dc voltage converter (SCVC) severely degrades the energy efficiency, performance, and robustness of the VLSI system. In this paper, a fully digital resistance modulation (FDRM) technique is proposed to reduce the output ripple of SCVC, which is scalable and compatible with the exiting ripple reduction methods. The proposed FDRM technique suppresses the impulsive charging and discharging effects in the SCVC operation by dynamically modulating its equivalent switch resistances, resulting in a reduced output ripple. The FDRM control signals can be generated from simple logic gates with the interleaved clock signals, realizing a low implementation complexity. The proposed FDRM technique was verified by a fully integrated SCVC in 180-nm CMOS process with an active area of 0.93 mm2. The measurement results show that the SCVC prototype with the proposed FDRM technique achieves an averaged ripple reduction of 31.6% and a peak conversion efficiency of 88.96% under a loading range of 95–190 $\mu \text{A}$. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low-power dual-mode automatic sleep staging processor design using a neural-network (NN)-based decision tree classifier to enable real-time, long-term, and flexible sleep monitoring. The ultra-low-power feature is achieved by an algorithm-hardware co-design approach that jointly considers optimization opportunities across the algorithm, architecture, and circuit levels to minimize power consumption; consequently, the first sub-10- $\mu \text{W}$ NN-based automatic sleep staging processor is realized. The dual-mode NN models are trained by an open-source large-scale dataset. The default mode achieves 81.0% classification accuracy based on two signals of one electroencephalography (EEG) signal and one electromyography (EMG) signal, and the compact mode achieves 78.5% accuracy based on only one EEG signal. In addition, the proposed design was verified using the National Taiwan University Hospital (NTUH) dataset, for which 81.1% and 77.1% accuracy is achieved in the default and the compact modes, respectively. A prototype chip using a 180-nm CMOS process occupies a total area of 11.74 mm2 and operates at 10 KHz while consuming 4.96 $\mu \text{W}$ at 1.2 V. [ABSTRACT FROM AUTHOR]

Ultra-low-voltage (ULV) satisfies the energy-constraint on-die acceleration of parallel processing in battery-powered Internet-of-Things applications. However, ULV brings serious leakage energy, throughput reduction, and delay variation issues. Parallel bit-serialization remarkably reduces leakage energy and enhances area efficiency; however, extremely reduced critical path aggravates delay variation makes bit-serial operation not feasible to ULV design. In this paper, we propose a balanced-bit-serial adder (BBSA) as a basic unit of parallel-balanced-bit-serialization (PBBS) operation, which leverages timing borrowing to mitigate delay variation. In addition, we propose two latches to improve the effectiveness of timing borrowing and ease the area and power overhead of BBSA. The proposed BBSA is verified in TSMC 40-nm CMOS technology. Compared with the flip-flop-based bit-serial adder, energy consumption of BBSA is saved by 40% and area efficiency is improved by 15% as well. As a practical demonstration, we present a reconfigurable PBBS single instruction multiple data (SIMD) vector processing tile. The post-layout simulation shows that the proposed design has advantage of overall area efficiency and has significant energy saving as compared with the state-of-art ULV SIMD tile. [ABSTRACT FROM PUBLISHER]