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Nowadays, cluster tools are extensively used for many wafer manufacturing processes, such as coating, lithograph, developing, etching, deposition, and testing. Traditional process modules in cluster tools can execute a single operation only. With the rapid development of equipment design, multifunctional process modules (MPMs) are equipped to serve for processing multiple operations together just like a single operation. With different wafer processing parameters, MPMs may be set for processing multiple operations together or processing just a single operation to form different schedules so as to maximize the productivity. Thus, it is highly desired to find an efficient scheduling method to quickly adapt to wafer processing parameter changes for productivity maximization by taking the advantages of MPMs. To tackle this issue, a deadlock-free Petri net (PN) model is developed to describe the behavior of a single-arm cluster tool. Based on the evolving mechanism of the PN model, two algorithms are developed to calculate the makespan for completing a given number of wafers. Then, an adaptive scheduling method is presented to set the functions of MPMs to minimize the makespan. Finally, experimental results show the efficiency and effectiveness of the proposed method.

With the circuit width of a wafer being decreased below 10 nanometers, it is important to reduce the wafer delay time in a process module as much as possible since too long wafer delay time has negative influence on the wafer quality. To do so, based on a Petri net model, we examine the characteristic of the robot wait time under the steady state by an earliest starting strategy. It is found that a unique steady state is reached by such a strategy, leading to inevitable wafer delays in the system. Then, a robot-waiting-time-controlled method is presented to reduce the wafer delays as much as possible by appropriately regulating the robot idle time. Finally, two industrial examples show that the robot-waiting-time-controlled method outperforms the earliest starting strategy in terms of the wafer delay reduction.