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In conventional inverters, the linear modulation range is limited to a maximum voltage space vector radius of 0.866 times the dc link voltage ($\text{V}_\text{dc}$), which corresponds to a maximum peak fundamental phase voltage of 0.577 $\text{V}_\text{dc}$. Beyond this, the inverter enters the overmodulation region, where the operation transitions to a six-step mode causing the voltage space vector to trace a hexagonal locus. This results in phase voltage waveforms with significant lower order harmonic content leading to torque ripples in the motor shaft and undesired harmonic losses. Thus, the achievable speed range of the induction motor in the linear modulation range is effectively limited to 90.5% of its full base speed. In contrast, the proposed five-level inverter topology generates a circular voltage space vector locus with a radius of up to 0.955 $\text{V}_\text{dc}$ resulting in a maximum peak fundamental phase voltage of 0.637 $\text{V}_\text{dc}$. Thus, the linear modulation range is extended to full base speed and is independent of the load power factor. The proposed power circuit is based on two standard three-level neutral point clamped inverters and can be realized by two readily available three-level NPC inverter IC packages. Standard space vector pulsewidth modulation techniques can be employed for switching pulse generation.

This article proposes an 18-switch five-level inverter topology for induction motor (IM) drives, enabling an extended linear modulation range (LMR) till full base speed. The power circuit consists of a conventional NPC three-level inverter and a standard two-level inverter feeding the opposite phase winding ends of an open-ended winding IM. The proposed inverter achieves a voltage space vector radius of $0.955~{V}_{\text {dc}}$ and a maximum peak fundamental phase voltage of $0.637~{V}_{\text {dc}}$ in its LMR compared to a conventional five-level inverter with the corresponding figures of 0.866 and $0.577~{V}_{\text {dc}}$ , respectively. This improvement arises from the fact that in the overmodulation region spanning from 0.577 to $0.637~{V}_{\text {dc}}$ , the standard five-level inverter operates in a six-step mode, resulting in the voltage space vector trace a hexagonal path producing a lower-order harmonic-rich phase voltage. The proposed power circuit effectively addresses this issue by ensuring a circular locus for the voltage space vector up to a radius of $0.955~{V}_{\text {dc}}$ resulting in a maximum peak fundamental voltage of $0.637~{V}_{\text {dc}}$ . Consequently, it extends the linear speed range of the motor to the full base speed without lower-order harmonic problems.

This work presents a hybrid seven-level dual inverter scheme with increased linear modulation range. The hybrid inverter structure is formed by supplying the load from primary side by using a cascaded structure of a two-level inverter and H-bridge (HB) and secondary side of the load is supplied by a floating-capacitor-fed two-level inverter. The combination of primary two-level space vector structure (SVS) with secondary two-level SVS and primary three-level SVS of HB form a seven-level SVS that can further be extended to an eight-level hexagonal SVS. This structure then reduced to a 12-sided eight-level SVS to avoid exceeding motor phase voltage rating. Subsequently by using this eight-level SVS in an unique pulsewidth modulation mode, the proposed topology can increase the modulation range linearly from $0.577V_{\text{dc}}$ to $0.637V_{\text{dc}}$ peak phase fundamental voltage for any load power factor (pf), where dc-link voltage is $V_{\text{dc}}$. An 11$\%$ increase in modulation range ($0.637V_{\text{dc}}/0.577V_{\text{dc}}$) is possible devoid of lower order harmonics (predominantly $5{\text{th}}$, $7{\text{th}}$, $11{\text{th}}$, $13{\text{th}}$, etc.) in phase voltage for unity pf load in comparison to the conventional six-step operation of two-level and multilevel hexagonal SVS. To balance HB capacitors voltages in this work, a concept of indirect space vector redundancy is used. The efficacy of the proposed inverter scheme is verified through various experimental results at different steady-state and transient conditions.

This article proposes a multilevel 24-sided polygonal voltage space vector structure (VSVS), eliminating lower order harmonics up to 19th order and suppressing higher order harmonics in motor phase voltage throughout the modulation range. Unlike switched average vectors in literature, the proposed scheme generates real active vectors that have the advantage of less switching frequency operation. The proposed VSVS consists of two concentric polygons divided into similar triangles resulting in a simple modulation algorithm. Instantaneous error in phase voltage reduces due to the multilevel property of the proposed VSVS. The proposed scheme extends the dc bus utilization and linear range of operation. The proposed scheme is implemented on an open-end winding induction motor fed with primary and secondary inverters from either end. This article also presents a modulating wave-based method to compute nearest vector timings using sampled reference waves only. Unlike conventional methods, the proposed timing calculation method does not require trigonometric operations, sorting algorithms, and iterative search algorithms. Experimental verification of the proposed scheme is performed to validate the concept. Switching loss and Fourier analysis comparison with some existing schemes is also presented.

The voltage drift control of series-connected capacitors across a single dc-link is the major challenge for a multineutral point-clamped (NPC) converter. This drifting is caused due to uneven currents drawn from the neutral points (NPs) during the PWM operation. This work presents the working principle of instantaneous voltage control of “ $n$ ” dc-link series-connected capacitors for an induction machine load. The mechanism of instantaneous voltage balancing is realized by ensuring zero instantaneous currents at each dc-link NP. To get zero instant currents at a dc-link NP branch, the phase terminals tapping on the dc-link are manipulated with the help of cascaded hybrid bridges (CHBs). Charge balancing of CHB capacitors is also taken care of by proper utilization of pole voltage redundancies. The detailed results are presented for a small-scaled inverter (nine-level) with three NPs (four dc-link capacitors). The simulation and experimental results reflect the capability and limitations of such inverters. The results are presented at all modulation indexes operated under low-power-factor (LPF) and high-power-factor (HPF) load conditions. It is found that the linear modulation range (LMR) can be increased to full base speed even for an HPF load.

An inverter circuit to generate a 13-level 24-sided polygonal voltage space vector structure (VSVS) comprised of 288 real active vectors and a zero vector is proposed in this article. The proposed scheme eliminates lower order harmonics up to 19th order and suppresses higher order harmonics from motor phase voltage in the full modulation range. The 48-step operation of the proposed scheme highly improves phase voltage quality at full speed. The dc bus utilization of the proposed scheme is improved to 99.42% compared to 90.6% multilevel hexagonal VSVS. The proposed topology has inherent capacitor balancing in every sampling interval at any loading condition using pole voltage redundancies. Multilevel property of the proposed scheme reduces instantaneous error in phase voltage compared to two-level 24-sided polygonal VSVS. Generation of real active vectors reduces instantaneous error in phase voltage and reduces switching frequency compared to switched average techniques existing in the literature. Fault-tolerant feature of the proposed scheme improves the availability of the drive system. Experimental results are provided to validate the steady-state operation, capacitor balancing, transient performance, and fault-tolerant capability of the proposed scheme. The comparison of switching loss and harmonic performance of the proposed scheme is performed with existing topologies.