Search

This brief reports a novel low-power 30GHz LNA in 22nm FDSOI CMOS technology. The LNA is based on an active network with CMOS inverting amplifier stages, and input and output feedforward impedance matching networks. It exhibits a peak gain of 11.4 dB, a noise figure of 5.8 dB, with a record power consumption of 0.52 mW from a 0.8 V supply. Owing to its circuit topology, the LNA is compact in size and its core area amounts to $0.20\times0.22$ mm2.

This brief reports a compact DC-110GHz single-pole single-throw (SPST) switch in 22nm FDSOI CMOS technology. The switch adopts solely three n-MOSFETs, two of them with a special device option to reduce the substrate parasitic effects, and a third n-MOSFET in parallel to the gate resistance of the series n-MOSFET to improve isolation. Unlike prior wideband mm-wave switches, it does not make use of any large passive components, such as spiral inductors, transformers and transmission lines, which are prone to large parasitic effects, including losses, and require large area on silicon. Altogether, the novel switch circuit allows a very compact design, low losses and high isolation performance. The switch exhibits an insertion loss lower than 3.1 dB, an isolation better than 22 dB, and a return loss better than 12 dB, over the entire frequency range from DC to 110 GHz. The area on die amounts to $160~\mu \text{m}^{2}$ , that is up two or more orders of magnitude smaller than prior wideband mm-wave SPST switches.

Dear TCAS-I Readers,

This paper reports a novel systematic theory of the noise invariants of two-port linear noisy networks under lossless reciprocal input and output impedance transformations. The theory clarifies the relationship between the circuit theory of linear noisy networks and the theory of four noise parameters, which are widely applied in the design of low-noise amplifiers (LNAs). In particular, we prove that the fundamental noise invariants under input and output impedance transformations are the eigenvalues of a permuted version of the noise correlation matrix and that there is no feedback operation that preserves them. Known invariants, such as the minimum equivalent noise temperature ${T}_{{N}{min}}$ and ${N}$ , may be expressed in terms of such eigenvalues. In addition, we provide a complete characterization of the four noise parameters of two-port passive dissipative networks in terms of their gain parameters and derive the condition under which the invariant ${4N}{T}_{{0}}{/}{T}_{{N}{min}}$ of passive nonreciprocal networks is lower than two. We also extend the theory of special noise invariants to LNAs with lossy input matching network. Overall, the impact of the findings emerging from the theory is highlighted through theorems, remarks, circuit examples, and studies on widespread design methodologies. [ABSTRACT FROM AUTHOR]

The transformer-based input integrated matching allows the realization of the simultaneous optimum noise and maximum power transfer input impedance matching in cascode amplifiers by exploiting the mutual coupling between the two spirals of an integrated transformer. This technique has been adopted to design LNAs operating in the microwave and millimeter-wave frequency ranges; however, the analytical proofs are still missing. This paper addresses for the first time a complete and in-depth study of the circuit topology and design technique in order to provide the analytical proofs. In-depth analyses are also used to get useful circuit insights, derive effective design equations, and carry out a direct comparison with the most widespread cascode low-noise amplifier with inductive degeneration through circuit design under the same conditions. [ABSTRACT FROM PUBLISHER]

This paper reviews recent developments of semiconductor integrated radar for modern sensing applications. It focuses on a few representative works of integrated radar sensor chips that operate in the continuous-wave mode and the ultra-wideband pulse mode. The benefits of solid state science and technology to modern radar-on-chip solution are clearly demonstrated through those examples. The paper also presents some commercial application case studies, and discusses the outlook of integrated radar solution and the corresponding need from future semiconductor technologies.

System-on-chip (SoC) miniaturization of radiometric sensors could dramatically improve quantitatively the study of Earth’s atmosphere in the microwave- and millimeter-wave frequency regions, enabling cost and weight reductions both for ground- and space-based observation instruments. This paper reports the analysis, design, implementation, and experimental characterization of the first K-band SoC Dicke radiometric receiver implemented in a commercial silicon–germanium technology under Space evaluations. The radiometric receiver exhibits a responsivity of about 760 kV/W and a noise equivalent power of about 232 fW/ $\surd $ Hz at the center frequency of 25.75 GHz. For a bandwidth of 2.5 GHz, the system achieves a resolution of 9 K for a relatively short integration time (1 s), 2.8 K for a medium integration time (10 s), and 0.9 K for a relatively long integration time (100 s). [ABSTRACT FROM AUTHOR]

A 50 GHz cross‐coupled differential‐pair oscillator with a high‐Q active inductor in the LC tank has been designed and fabricated in 65 nm bulk complementary metal‐oxide semiconductor (CMOS) technology. The principle of operation is explained and a complete theoretical study is carried out. The analytical expressions for the open loop transfer function, oscillation frequency, start‐up condition, tank impedance, and phase noise are derived. The results of the analytical study are compared with those obtained by SpectreRF simulations in the Cadence design environment. Measurement results of the stand‐alone mm‐wave active inductor show an equivalent inductance of 133 pH with a quality factor exceeding 400 at 50 GHz, demonstrating experimentally the implementation of high‐Q active inductors operating at the millimeter waves in CMOS technology. The measurement results of the oscillator show a phase noise of −85 dBc/Hz at 1 MHz frequency offset from the carrier when the active inductor is switched off and −91 dBc/Hz when it is switched on, leading to a phased noise reduction of 6 dB. This original manuscript expands and extends the contents reported in the short conference paper “50 GHz LC‐active oscillator in 65 nm CMOS” presented at the 2015 IEEE 15th Mediterranean Microwave Symposium (MMS), selected and invited for publication in Radio Science—Special Issue on “Innovative Microwave Devices, Methods, and Applications”A 50 GHz active‐LC oscillator in 65 nm CMOS has been designed and characterized experimentallyA complete theoretical circuit analysis of the proposed oscillator has been carried out extensively in large details A 50 GHz oscillator with a high‐Q active inductor in the LC tank has been designed and fabricated in 65 nm bulk CMOS technology. The principle of operation is explained and a complete theoretical study is carried out. The analytical expressions for the open loop transfer function, oscillation frequency, start‐up condition, tank impedance and phase noise are derived. The results of the analytical study are compared with those obtained by simulations. Measurement results of the stand‐alone mm‐wave active inductor show an equivalent inductance of 133 pH with a quality factor exceeding 400 at 50 GHz, demonstrating experimentally the implementation of high‐Q active inductors operating at the millimeter‐waves in CMOS technology. The measurement results of the oscillator show a phase noise of −85 dBc/Hz at 1 MHz frequency offset from the carrier when the active inductor is switched off and −91 dBc/Hz when it is switched on, leading to a phased noise improvement of 6 dB.

A low-complexity fully integrated ultrawideband (UWB) monocycle pulse generator realized in 90-nm CMOS technology by ST-Microelectronics is presented. The circuit provides a monocycle pulse when activated by a negative edge of an external trigger signal provided by a microcontroller by exploiting the operating principle of nonlinear waveform shapers. This pulse generator represents a building block of an innovative wearable system-on-chip UWB radar on silicon for cardiopulmonary monitoring. On-chip measurements show that the pulse generator provides monocycle pulses with a duration time equal to 380 ps and a peak-to-peak amplitude of 660 mV (including the losses of the microprobes, cables, and electrostatic-discharge-protected pads), which are in very good agreement with the postlayout simulations. The power consumption is 19.8 mW from a 1.2-V power supply. [ABSTRACT FROM PUBLISHER]

Welcome to the 2017 Special Issue on the IEEE Circuits and Systems Society (CASS) Regional Flagship Conferences, a collection of selected papers presented at the 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), held in Jeju, South Korea, October 25–28, 2016, the 23rd IEEE International Conference on Electronics Circuits and Systems (ICECS 2016), held in Monte Carlo, Monaco, December 11–14, 2016, and the 8th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2017), held in Bariloche, Argentina, February 20–23, 2017. In APCCAS 2016, 212 papers were presented, selected from 310 papers submitted; in ICECS 2016, 191 papers were presented, selected from 353 papers submitted; in LASCAS 2017, 70 papers were presented, selected from 172 papers submitted. [ABSTRACT FROM AUTHOR]