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Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~106 years. [ABSTRACT FROM AUTHOR]

Today, silicon microchips underlie every aspect of digital computing. But their dominance was never a foregone conclusion. Throughout the 1950s, electrical engineers and other researchers explored many alternatives to making digital computers. One of them seized the imagination of the U.S. National Security Agency (NSA): a superconducting supercomputer. Such a machine would take advantage of superconducting materials that, when chilled to nearly the temperature of deep space-just a few degrees above absolute zero-exhibit no electrical resistance whatsoever. This extraordinary property held the promise of computers that could crunch numbers and crack codes faster than transistorbased systems while consuming far less power. For six decades, from the mid-1950s to the present, the NSA has repeatedly pursued this dream, in partnership with industrial and academic researchers. Time and again, the agency sponsored significant projects to build a superconducting computer. Each time, the effort was abandoned in the face of the unrelenting pace of Moore?s Law and the astonishing increase in performance and decrease in cost of silicon microchips. [ABSTRACT FROM PUBLISHER]

The resonator-induced PHASE gate is a multiqubit controlIed-PHASE gate for fixed-frequency superconducting qubits. Through off-resonant driving of a bus resonator, statically coupled qubits acquire a state-dependent phase. However, photon loss leads to dephasing during the gate, and any residual entanglement between the resonator and qubits after the gate leads to decoherence. Here we consider how to shape the drive pulse to minimize these unwanted effects. First, we review how the gate's entangling and dephasing rates depend on the system parameters and validate closed-form solutions against direct numerical solution of a master equation. Next, we propose spline pulse shapes that reduce residual qubit-bus entanglement, are robust to imprecise knowledge of the resonator shift, and can be shortened by using higher-degree polynomials. Finally, we present a procedure that optimizes over the subspace of pulses that leave the resonator unpopulated. This finds shaped drive pulses that further reduce the gate duration. Assuming realistic parameters, we exhibit shaped pulses that have the potential to realize ~212 ns spline pulse gates and ~ 120 ns optimized gates with ~ 6 x 10-4 average gate infidelity. These examples do not represent fundamental limits of the gate and, in principle, even shorter gates may be achievable. [ABSTRACT FROM AUTHOR]

The article presents the discussion on Quantum Device Lab at ETH Zurich taking a major step towards fault-tolerant quantum computing demonstrating the protection of quantum states against unavoidable decoherence.