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The state-of-the-art 4H-SiC MOSFETs still suffer from performance (low channel-carrier mobility and high threshold voltage) and reliability (threshold voltage instability) issues. These issues have been attributed to a large density of electrically active defects that exist in the SiO 2 –SiC interfacial region. This paper reviews the earlier and the latest results about the responsible defects for the performance and reliability issues of SiC MOS devices, in the context of the evolution of physical understanding of these defects. The aim of this critical review is to clarify possible confusions due to inconsistencies between the earlier and the latest results. Specific clarifications relate to the physical position of the active defects (whether they are located at or near the SiO 2 –SiC interface) and the energy position of their energy levels (above or below the bottom of conduction band). [ABSTRACT FROM AUTHOR]

In this paper, we studied the enhancement of the breakdown voltage in the 4H–SiC MESFET–MOSFET (MES–MOSFET) structure which we have proposed in our previous work. We compared this structure with Conventional Bulk-MOSFET (CB-MOSFET) and Field plated Conventional Bulk-MOSFET (FCB-MOSFET) structures. The 4H–SiC MES–MOSFET structure consists of two additional schottky buried gates which behave like a Metal on Semiconductor (MES) at the interface of the active region and substrate. The motivation for this structure was to enhance the breakdown voltage by introducing a new technique of utilizing the reduced surface field (RESURF) concept. In our comparison and investigation we used a two-dimensional device simulator. Our simulation results show that the breakdown voltage of the proposed structure is 3.7 and 2.9 times larger than CB-MOSFET and FCB-MOSFET structures, respectively. We also showed that the threshold voltage and the slope of drain current ( I D ) as a function of drain–source voltage ( V DS ) for all the structures is the same. [ABSTRACT FROM AUTHOR]

Measurements of the near-interface oxide traps (NIOTs) aligned to the conduction band of silicon-carbide (SiC) are of particular importance as these active defects are responsible for degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this brief, a new method for measurement of the active NIOTs with energy levels aligned to the conduction band is proposed. The method utilizes transient-current measurements on 4H-SiC MOS capacitors biased in accumulation. Nitrided oxide and dry oxide are used to illustrate the applicability of the proposed measurement method. [ABSTRACT FROM AUTHOR]

ABSTRACT In this paper, we employ the Reduced Surface Field technique in metal semiconductor field effect transistors (MESFETs) by a P-type region above the active layer near gate (PR-MESFET). Electric field distribution can be made more uniform by a new depletion region in the active layer of the proposed structure that is created by a P-type region. Therefore, the electric field peak at the gate edge decreases, and the breakdown voltage increases. On the basis of our simulation results, the breakdown voltage increases as compared with the conventional bulk 4H-SiC MESFET (CB-MESFET) and the spacer bulk 4H-SiC MESFET (SB-MESFET). Detailed numerical simulations demonstrate that for proposed structure due to decrease in parasitic gate-to-drain capacitor, maximum oscillation frequency increases with respect to SB-MESFET. Our simulation results show that output current slightly decreases in comparison with CB-MESFET. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Near-interface traps (NITs) with energy levels aligned to the conduction band and spatially located close to the SiO2/SiC interface are responsible for significant degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this paper, we investigate fast trapping and detrapping of the conduction-band electrons by NITs with energy levels localized between 0.13 and 0.23 eV above the bottom of the conduction band. The trapping and detrapping times were estimated to be in the range between the resolution limit of tens of nanoseconds and $1~\mu \text{s}$ by measuring the current through n-type MOS capacitors in response to a ramped voltage in the accumulation region. [ABSTRACT FROM AUTHOR]