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This article provides a quantitative and qualitative evaluation of the role of interconnection directionality in a general class of quadratic performance metrics for double-integrator networks. We first develop an analysis framework that can be used to evaluate the quadratic performance metrics of networks defined over a general class of directed graphs. A comparison between systems whose directed graph Laplacians are normal and their undirected counterparts unveils an interplay between the interconnection directionality and the control strategy that determines network performance. We show that directionality can significantly degrade performance; however, well-designed feedback can exploit directionality to mitigate this degradation or even improve performance. [ABSTRACT FROM AUTHOR]

The performance of a biologically plausible spiking neural network (SNN) largely depends on the model parameters and neural dynamics. This article proposes a parameter optimization scheme for improving the performance of a biologically plausible SNN and a parallel on-field-programmable gate array (FPGA) online learning neuromorphic platform for the digital implementation based on two numerical methods, namely, the Euler and third-order Runge–Kutta (RK3) methods. The optimization scheme explores the impact of biological time constants on information transmission in the SNN and improves the convergence rate of the SNN on digit recognition with a suitable choice of the time constants. The parallel digital implementation leads to a significant speedup over software simulation on a general-purpose CPU. The parallel implementation with the Euler method enables around $180\times $ ($20\times $) training (inference) speedup over a Pytorch-based SNN simulation on CPU. Moreover, compared with previous work, our parallel implementation shows more than $300\times $ ($240\times $) improvement on speed and $180\times $ ($250\times $) reduction in energy consumption for training (inference). In addition, due to the high-order accuracy, the RK3 method is demonstrated to gain $2\times $ training speedup over the Euler method, which makes it suitable for online training in real-time applications. [ABSTRACT FROM AUTHOR]

Associative processors, while ideal for vector-based applications, have been limited in their use mainly due to area and energy considerations. This reality is changing due to the advent of ultra-dense resistive memories (RRAMs), allowing for area efficient implementations of in-memory associative processors. However, with the high levels of integration, issues related to power density become the major bottleneck. In this paper, we investigate approximate computing in RRAM-based associative processors as a means of enhancing energy efficiency for in-memory associative processors. A case study of a wireless communication system is considered, where fast Fourier transform (FFT) modules are widely used. The proposed manager adjusts the bit width based on the channel SNR, aiming at achieving the desired performance at a reduced energy consumption. An analytical model of system performance under the reduced bit width induced noise is presented. Based on this model, an adaptive bit width adjustment algorithm is presented that utilizes the received SNR estimates to find the optimal bit width that achieves the desired performance goals. Simulation results show that the proposed algorithm can achieve up to 45% energy savings as compared to wireless communication systems using conventional RRAM FFT associative processor. [ABSTRACT FROM AUTHOR]

This paper presents three lifting structures of Daubechies-8 (also known as D8) wavelet transform using efficient factorization of the polyphase matrix. All new filter coefficients are optimally mapped with integers resulting in low cost hardware implementation. We first derive the polyphase matrices using a factorization algorithm, which forms the basis of multiple lifting structures of D8. A theoretical framework is then derived and proven experimentally to eliminate the scaling stage of the algorithm that incurs computation error in conventional integer-based wavelets. This elimination of the scaling stage makes the proposed architecture lossless. Also due to the optimum integer mapping, the 8-bit implementation of our schemes produces very similar results than that of the classical double-precision D8 filter. Finally, we compare our results with other existing lifting wavelets to demonstrate the advantage in terms of lower cost, losslessness and improved performance. [ABSTRACT FROM AUTHOR]

This paper proposes a method to maintain the strong connectivity property of a mobile robot ad hoc network in the presence of disturbances or additional control goals. Each robot has a communication range modeled by an $n$-dimensional sphere centered at the robot. The spheres for different robots may have different radii, resulting in a directed communication network. This paper is based on two concepts. The first is the structure of the Perron vector for reducible stochastic matrices. The second is the design of nonlinear controllers that ensure that two robots remain within a certain distance of each other despite disturbances. The results are supported by analysis and simulations. [ABSTRACT FROM AUTHOR]

This paper presents novel designs of static dual-edge-triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of the presented flip-flops is their low energy dissipation due to glitches at the input. Novel DET flip-flops are compared to existing DET flip-flops using simulation in a high performance 28 nm CMOS technology and are shown to have superior characteristics such as power and power-delay product (PDP) for a range of switching activities. Extensive Monte Carlo and voltage scaling simulations are performed to show that the presented designs are robust under PVT variations. [ABSTRACT FROM PUBLISHER]

Measured data or states for a nonlinear dynamic system is usually contaminated by outliers. Identifying and removing outliers will make the data (or system states) more trustworthy and reliable since outliers in the measured data (or states) can cause missed or false alarms during fault diagnosis. In addition, faults can make the system states nonstationary needing a novel analytical model-based fault detection (FD) framework. In this paper, an online outlier identification and removal (OIR) scheme is proposed for a nonlinear dynamic system. Since the dynamics of the system can experience unknown changes due to faults, traditional observer-based techniques cannot be used to remove the outliers. The OIR scheme uses a neural network (NN) to estimate the actual system states from measured system states involving outliers. With this method, the outlier detection is performed online at each time instant by finding the difference between the estimated and the measured states and comparing its median with its standard deviation over a moving time window. The NN weight update law in OIR is designed such that the detected outliers will have no effect on the state estimation, which is subsequently used for model-based fault diagnosis. In addition, since the OIR estimator cannot distinguish between the faulty or healthy operating conditions, a separate model-based observer is designed for fault diagnosis, which uses the OIR scheme as a preprocessing unit to improve the FD performance. The stability analysis of both OIR and fault diagnosis schemes are introduced. Finally, a three-tank benchmarking system and a simple linear system are used to verify the proposed scheme in simulations, and then the scheme is applied on an axial piston pump testbed. The scheme can be applied to nonlinear systems whose dynamics and underlying distribution of states are subjected to change due to both unknown faults and operating conditions. [ABSTRACT FROM AUTHOR]

Regulation of gene expression stages within a cellular creature deals with all the complexities and functionalities of the organism. These genetic information processing activities inside the cell can imitate the specific operations carried out by different combinations of semiconductor devices. Appropriate gene regulation is the basis of correct system biological functionality within all living organisms. Any biochemical aberrations (mutations) in a cell cycle which are not diminished genetically can result in progressive cellular dysfunction. Controlling mutations can be approached by realizing a “silicon mimetic” electronic circuit emulating the gene expression stages. This paper presents an integrated circuit model mimicking the post-transcriptional stages in gene expression regulated by microRNAs and Proteasome. The mRNA degradation by microRNA is modeled using emitter degeneration, while the protein degradation is modeled by a mixed-signal CMOS circuit. The effect of enzymes in the degradation reaction is also explored using a “chemo-inductor.” Probabilistic analysis using Monte Carlo simulations indicates that the proposed staged gene circuit model is also robust in an environment of stochastic biochemical reactions. The model is found to be in close agreement with experimentally reported data. [ABSTRACT FROM PUBLISHER]

It has been known for at least five decades that control theory can be used to study iterative algorithms. However, little work can be found in the control systems literature on numerical algorithms, especially on the study of finite precision effects. In this technical note, we consider numerical iterative algorithms in finite precision as dynamical systems and study the effects of finite precision using control theory. By using the control tools of input-to-state stability and results from the study of quantization in control systems, we present new systematic ways to find bounds on the forward error for iterative algorithms. The advantages of the proposed schemes are shown by applying them to find bounds for the classical iterative methods for solving a system of linear equations. [ABSTRACT FROM AUTHOR]

This paper proposes a novel solution to make asynchronous handshake interfaces tolerant to crosstalk-glitch propagation (GP). This study leverages our recently proposed crosstalk-glitch modeling technique for asynchronous systems, which models the crosstalk GP in asynchronous interfaces. In this paper, a novel set of solutions to quench the GP is proposed. This set of solutions is called crosstalk-glitch gating, as the quenching is obtained by using carefully generated control signals. A step-by-step method is recommended to apply crosstalk-glitch gating to conventional asynchronous handshake interfaces. Transistor-level electrical simulations demonstrate that our method effectively generates crosstalk-glitch gate-controlling signals. In comparison with contemporary signal-integrity management techniques, our gating methodology can be applied to fewer nodes and earlier in the design cycle. [ABSTRACT FROM PUBLISHER]

This paper characterizes the potentially catastrophic effect of crosstalk glitches on representative circuit implementations of two widely used asynchronous protocols. It is demonstrated that the crosstalk glitches can induce false events, which can undesirably propagate into asynchronous interface circuits and may cause system failure. Conventionally, to a circuit designer, glitch propagation (GP) due to aggressor-to-quiet-line crosstalk (AQX) in asynchronous handshake schemes can only be observed through circuit-level analysis/simulation. In this paper, circuit-level analysis is first performed to prove that even optimized conventional asynchronous circuits allow crosstalk glitches produced over moderate-length interconnects (1.5 mm) to propagate. This is a precursor to a more problematic crosstalk glitch occurrence due to further scaling of technologies. To warn the digital designers from GP due to AQX, a novel modeling technique is proposed. This modeling method works at the logic level to facilitate asserting asynchronous interface robustness to crosstalk glitches. This model can accurately identify the possibility of intrinsic (to the asynchronous interface) crosstalk GP in asynchronous circuits at the logic level and, hence, provides a foundation to formally verify such circuits. To our knowledge, this is the first work on modeling GP due to AQX at the logic level for asynchronous circuits. [ABSTRACT FROM PUBLISHER]

This paper discusses the formulation of "silicon mimetic" mixed-signal integrated circuit (IC) models for bio-cellular genetic circuits and state machines that utilize the rich variety of deoxyribonucleic acid and protein regulatory interactive pathways. A novel mixed-signal circuit model is reported for determining the state transitions of a genetic circuit. Using hysteretic electronic switch analogues for messenger ribonucleic acid transcription, a genetic state machine can be auto-triggered resulting in the self-timed transformation of an existing state of gene expression into another desired state of gene expression. Such an electronic model of genetic circuits and state machines focuses on the central theme of post-genomic research into gene-protein connectivity based cellular phenomenon. Novel synthetic genetic circuits designed using the mature resources of IC simulation will result in important outcomes for biomaterials based computation, bionanotechnology, as well as, gene and cell therapy. [ABSTRACT FROM AUTHOR]

A new nonpipelined bit-parallel-shifted polynomial basis multiplier for GF(2n) is presented. For some irreducible trinomials, the space complexity of the multiplier matches the best results available in the literature, and its gate delay is equal to TA + ⌈log2 n⌉ TX, where TA and TX are the delay of one two-input AND and XOR gates, respectively. To the best of our knowledge, this is the first time that the gate delay bound TA + ⌈log2 n⌉ TX is reached. For some irreducible pentanomials, its gate delay is equal to TA + (1 + ⌈log2 n⌉)TX. NIST has recommended five binary fields for the elliptic curve digital signature algorithm applications: GF(2163), GF(2233), GF(2283), GF(2409), and GF(2571), but no irreducible trinomials exist for three degrees, viz., 163, 283 and 571. For the three corresponding binary fields, we show that the gate delay of the proposed multiplier is TA + (1 + ⌈log2 n⌉)TX. This result outperforms the previously known results. [ABSTRACT FROM AUTHOR]

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-μm 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of ≈ 60 dB ohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 μA. The output noise voltage spectral density was 12 nV/√HZ (with a peak of ≈ 25 nV/s/√HZ), while the input-referred noise current spectral density was below 20 pA/√HZ within the amplifier frequency band. The amplifier consumes only around 5 mA from a 33-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents an efficient hybrid energy harvesting interface to synergistically scavenge power from electromagnetic (EM) and piezoelectric (PE) sources, and drive a single load. The EM harvester output is rectified through a self-powered active doubler structure, and stored on a storage capacitor. The stored energy is then transferred to the PE harvester to increase the damping force and charge extraction. The total synergistically extracted power from both harvesters is more than the power obtained from each independently. The hybrid operation is validated through a compact and wearable platform that includes custom designed EM and PE harvesters for scavenging energy from human motion. The system supplies 1–3.4 V output for powering up wireless sensor nodes with a wide range of vibration frequency, and generates between 1– $100~\mu \text{W}$ at 90% maximum power conversion efficiency. The solution has superior power generation performance compared to previous stand-alone systems in the literature. [ABSTRACT FROM AUTHOR]