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This report describes The University of Texas Student Cluster Competition team’s effort to reproduce the results of “MemXCT: memory-centric X-ray CT reconstruction with massive parallelization” (Hidayetoğlu et al., 2019). The article details a new memory-centric approach that reconstructs X-ray computed tomography (XCT) from noisy raw data. In our reproduction experiments, we utilized Microsoft Azure’s CycleCloud tool to provision, orchestrate, and manage our computing cluster in the cloud. In particular, we scheduled and benchmarked reconstruction workloads using Azure’s CPU-based HC44rs and GPU-based NC12s v2 virtual machine (VM) types to evaluate the scalability properties of the reconstruction approach and the performance differences between architectures. The HC44rs VMs contained 44 Intel Xeon Platinum cores, while the NC12s v2 VM was equipped with two NVIDIA P100 GPUs. We used a recent version of Intel’s compiler stack with the MKL library for our CPU code along with CUDA 11.1 on GPUs. Overall, our results confirm the findings of the original article, demonstrating similar acceleration on GPUs and scalability properties on CPUs. Digital artifacts from these experiments are available at: 10.5281/zenodo.5598108 [ABSTRACT FROM AUTHOR]

This column discusses two awards given in 2014: the International Symposium on Computer Architecture Influential Paper Award, which was given to the authors of the paper "PipeRench: A Coprocessor for Streaming Multimedia Acceleration," and the Maurice Wilkes Award, which was given to Ravi Rajwar. [ABSTRACT FROM PUBLISHER]

The guest editors introduce the Top Picks and Honorable Mentions from the 2016 computer architecture conferences. [ABSTRACT FROM PUBLISHER]

This paper presents a smart and embedded multi-touch system for consumer electronics. The infrared (IR) camera is utilized to capture the coordinate of the IR blob from IR stylus or human finger in an emitted IR field. This system allows the consumer to easily convert large surface, projector screen, or conference table into multi-touch interface. The keystone distortion of IR camera is compensated by using homography. To improve the user experience, the calibration of homography is automatically triggered by accelerometer sensor. The special purpose (SP) processor with the parallel COordinate Rotation Digital Computer (CORDIC) architecture computes the observation-to-track association, and the computation result updates the motion status of each tracked trajectory. These motion data support the multi-touch tracking system to evaluate the sliding window of each tracked trajectory for reducing the tracking error. Additionally, the motion data are reused by the adaptive trajectory estimation (TE) system to smooth the touch trajectory and mitigate the measurement noise. This research presents multiple autonomous functions to provide a user-friendly multi-touch interface for consumer electronics. These include the automatic calibration system, the multi-touch tracking architecture with motion estimation system, and the adaptive TE system. [ABSTRACT FROM AUTHOR]

This column discusses the 2015 ISCA Influential Paper Award, which recognized "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations" by David Brooks, Vivek Tiwari, and Margaret Martonosi. [ABSTRACT FROM AUTHOR]

This article discusses the 2017 ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award, which was given to the 2002 ISCA paper, “Drowsy Caches: Simple Techniques for Reducing Leakage Power.” [ABSTRACT FROM AUTHOR]

While graphics remain central to the mission of the article titled "NVIDIA A100 Tensor Core GPU: Performance and Innovation", GPUs have becomethedefaultforhighperformanceandprogrammability in one solution, supporting a huge variety of scientific computing workloads and powering both neuralnetworktrainingandinference. GUESTEDITORS'INTRODUCTION BestPapersFromHotChips32 Priyanka Raina,StanfordUniversity,Stanford,CA,94305,USA CliffYoung,Google,PaloAlto,CA,94306,USA W elcome toour specialissue of IEEE Micro, which highlights the best presentations from Hot Chips 32, held virtually on August 16-18, 2020. Bridging between the general-purpose floatingpoint power of GPUs and the specialized application focus of neural network accelerators, "Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing" uses the extensibility of the RISC-V ISA to reduce control overheads and energycostsforneural-networkworkloads. [Extracted from the article]

Every year, the International Symposium on Computer Architecture (ISCA) recognizes the most influential paper published in the conference 15 years earlier, based on its impact on research, development, products, or ideas. [ABSTRACT FROM AUTHOR]

This column discusses the MICRO Test of Time Award, given to the most influential papers published in past MICRO conferences. The authors discuss the selection process for 2014 and the future, solicit nominations for 2015, and announce the 2014 award winners. [ABSTRACT FROM PUBLISHER]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

This special issue is a result of the enthusiastic response to the initiation of a new industry paper track at the 2020 International Symposium on Computer Architecture, as we could not accept all the great submissions to that track.1 We are excited to share our interest in commercial products with many industry colleagues who answered our call for papers. [ABSTRACT FROM AUTHOR]

This introduction to the special issue presents the 2014 top picks in computer architecture, along with 12 "honorable mention" papers. [ABSTRACT FROM PUBLISHER]

This large volume of special issue includes all regular papers presented at Embedded Systems Week (ESWEEK) 2018 that brings together three leading conferences (CASES, CODES+ISSS, and EMSOFT) in the embedded systems area. ESWEEK is a unique premier event that covers all aspects of embedded systems design and hardware/software architectures. ESWEEK presents a wide range of topics unveiling state-of-the-art techniques as can be found in this special issue. Following the journal-integrated publication model started last year, the three conferences conducted the journal-like two-stage peer-reviewed process before final decision. Acceptance rates have been about 25.5% for all conferences with a total number of 270 submissions to the journal track. [ABSTRACT FROM AUTHOR]

The article discusses deadlines for submission of manuscript of periodical on various topics related to architectures, algorithms and applications of software defined vehicular networks (SDVN). Topics discussed include security and privacy in SDVN; data offloading in SDVN and flexible architecture in SDVN.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM PUBLISHER]

This paper presents the theoretical keystone for a decentralization of model-based diagnosis by proving the equivalence between decentralized and centralized residual generation. The proof is based on structural analysis and graph-theoretical concepts. The second contribution of this paper is the design of a decentralized fault-focused residual generation scheme advantageously implementing a strategy of fault isolation on request. Algorithms are tested on the attitude determination and control system of a low Earth orbit satellite. [ABSTRACT FROM PUBLISHER]

Three-phase grid-connected inverter modeling depends on the equivalent resistance and inductance between the inverter and the grid. However, these parameters are not fixed during the operation of the inverter and vary with the operating conditions. In this paper, a new globally stable adaptive controller is proposed to estimate these values online and update the controller during its operation. A model reference adaptive system (MRAS) based on two fictitious quantities with no physical significance is utilized, namely $M = v \cdot i^*$ and $N = v^* \times i$ , where $v$ and $i$ are the steady-state values of voltage and current in synchronously rotating frame of reference. Detailed stability analysis of the proposed estimation technique has been presented using a Lyapunov energy function-based approach proving the global stability of the technique. Small-signal modeling and analysis of the proposed scheme has also been presented so as to understand the local dynamics of the system. The guidelines to select the parameter of the proposed MRAS system along with updating the controller are elaborated in this paper. Detailed simulation based on MATLAB/Simulink and PLECS, along with experimental studies through a Texas Instruments TMS320F28377S microcontroller, validates the feasibility of the proposed control architecture. [ABSTRACT FROM AUTHOR]

Accelerator-based chip multiprocessors (ACMPs), which combine application-specific HW accelerators (ACCs) with host processor core(s), are promising architectures for high-performance and power-efficient computing. However, ACMPs with many ACCs have scalability limitations. The ACCs’ performance benefits can be overshadowed by bottlenecks on shared resources of processor core(s), communication fabric/DMA, and on-chip memory. Primarily, this is rooted in the ACCs’ data access and the orchestration dependency. Due to very loosely defined ACC communication semantics, and relying on general architectures, the resources bottlenecks hamper performance. This paper explores and alleviates the scalability limitations of ACMPs. To this end, this paper first proposes ACMPerf, an analytical model to capture the impact of the resources bottlenecks on the achievable ACCs’ benefits. Then, this paper identifies and formalizes ACC communication semantics which paves the path toward a more scalable integration of ACCs. The semantics describe four primary aspects: 1) data access; 2) data granularity; 3) data marshalling; and 4) synchronization. Finally, this paper proposes a novel architecture of transparent self-synchronizing accelerators (TSS). TSS efficiently realizes our identified communication semantics of direct ACC-to-ACC connections often occurring in streaming applications. TSS delivers more of the ACCs’ benefits than conventional ACMP architectures. Given the same set of ACCs, TSS has up to $130 \times $ higher throughput and $78 \times $ lower energy consumption, mainly due to reducing the load on shared architectural resources by $78.3 \times $. [ABSTRACT FROM AUTHOR]

We demonstrate, for the first time, resistive RAM (RRAM) arrays where each cell can store 3 bits. Such full array-level demonstration is possible through special techniques (e.g., that exploit RRAM-specific characteristics of variations in cell resistances), presented in this paper, which efficiently allocate resistance range corresponding to each bit combination (required for proper write operation) while maintaining appropriate sensing margin (required for proper read operation). Our techniques are not restricted to 3 bits-per-cell only (and, in this paper, we demonstrate 2 bits-per-cell at the array level as well). Our measured results are based on multiple 4 Kbit arrays of 1T1R HfOx-based RRAM integrated in the back end of the line of 130-nm silicon CMOS technology. We achieve 3 bits-per-cell (2 bits-per-cell) RRAM with 11 (3) programing iterations on average. [ABSTRACT FROM AUTHOR]

The paper surveys the state of the art of task scheduling in Desktop Grid computing systems. We describe the general architecture of a Desktop Grid system and the computing model adopted by the BOINC middleware. We summarize research papers to bring together and examine the optimization criteria and methods proposed by researchers so far for improving Desktop Grid task scheduling (assigning tasks to computing nodes by a server). In addition, we review related papers, which address non-regular architectures, like hierarchical and peer-to-peer Desktop Grids, as well as Desktop Grids designed for solving interdependent tasks. [ABSTRACT FROM AUTHOR]

This paper presents InnovA, a cognitive architecture for creative problem solving in analog circuit design, e.g., topology creation (synthesis), incremental topology modification, and design knowledge identification and reuse. The architectural modules attempt to replicate cognitive human activities, like concept formation, comparison, and concept combination. The architecture uses multiple knowledge representations organized using topological similarity and causality information. Solutions are clustered, so that each cluster represents a specific set of performance tradeoffs, thus a fragment of the Pareto front in the solution space. New structural features are created through variation of existing features. New solutions are created by combining features from the same cluster, distinct clusters, and features that originate a new cluster. The related algorithms are discussed in this paper too. The architecture also incorporates modules mimicking the using of human emotions in memory formation and decision making, but these modules are still under development and are a main direction for our future work. This paper presents a number of examples to illustrate its using in various analog circuit design activities that are hard to be realized with traditional computational methods. [ABSTRACT FROM AUTHOR]

Detecting large animals on roadways using automated systems such as robots or vehicles is a vital task. This can be achieved using conventional tools such as ultrasonic sensors, or with innovative technology based on smart cameras. In this paper, we investigate a vision-based solution. We begin the paper by performing a comparative study between three detectors: 1) Haar-AdaBoost; 2) histogram of oriented gradient (HOG)-AdaBoost; and 3) local binary pattern (LBP)-AdaBoost, which were initially developed to detect humans and their faces. These detectors are implemented, evaluated, and compared to each other in terms of accuracy and processing time. Based on our evaluation and comparison results, we design a two-stage architecture which outperforms the aforementioned detectors. The proposed architecture detects candidate regions of interest using LBP-AdaBoost in the first stage, which offers robustness to false positives in real-time conditions. The second stage is based on support vector machine classifiers that were trained using HOG features. The training data are generated from our novel dataset called large animal dataset, which contains common and thermographic images of large road-animals. We emphasize that no such public dataset currently exists. [ABSTRACT FROM PUBLISHER]

The tridiagonal solver is an important kernel and is widely supported in mainstream numerical libraries. While parallel algorithms have been studied for many-core architectures, the performance of current algorithms and implementations is still hindered by input size sensitivity and cross-platform portability. In this paper, we propose a novel algorithm WM-pGE for the batched solution of diagonally dominant tridiagonal systems. The algorithm balances the key design objectives, including computation complexity, memory complexity, parallelism, and input size sensitivity, better than existing algorithms. Moreover, an elegant formulation is presented to show the implementation and cross-platform optimization without loss of efficiency and generality, by extracting the platform-dependent works into only four vector operators. The results from our batched tridiagonal experiments show that the proposed algorithm outperforms the prior work PCR-pThomas by 25% and 12% on NVIDIA Tesla V100 in single and double precision, respectively. On Intel KNL, our method achieves a 10% improvement in performance over PCR-pThomas in double precision. [ABSTRACT FROM AUTHOR]

This paper presents a deep architecture, called pyramidal semantic correspondence networks (PSCNet), that estimates locally-varying affine transformation fields across semantically similar images. To deal with large appearance and shape variations that commonly exist among different instances within the same object category, we leverage a pyramidal model where the affine transformation fields are progressively estimated in a coarse-to-fine manner so that the smoothness constraint is naturally imposed. Different from the previous methods which directly estimate global or local deformations, our method first starts to estimate the transformation from an entire image and then progressively increases the degree of freedom of the transformation by dividing coarse cell into finer ones. To this end, we propose two spatial pyramid models by dividing an image in a form of quad-tree rectangles or into multiple semantic elements of an object. Additionally, to overcome the limitation of insufficient training data, a novel weakly-supervised training scheme is introduced that generates progressively evolving supervisions through the spatial pyramid models by leveraging a correspondence consistency across image pairs. Extensive experimental results on various benchmarks including TSS, Proposal Flow-WILLOW, Proposal Flow-PASCAL, Caltech-101, and SPair-71k demonstrate that the proposed method outperforms the lastest methods for dense semantic correspondence. [ABSTRACT FROM AUTHOR]

Recent work has shown that convolutional networks can be substantially deeper, more accurate, and efficient to train if they contain shorter connections between layers close to the input and those close to the output. In this paper, we embrace this observation and introduce the Dense Convolutional Network (DenseNet), which connects each layer to every other layer in a feed-forward fashion. Whereas traditional convolutional networks with $L$ L layers have $L$ L connections—one between each layer and its subsequent layer—our network has $\frac{L(L+1)}{2}$ L (L + 1) 2 direct connections. For each layer, the feature-maps of all preceding layers are used as inputs, and its own feature-maps are used as inputs into all subsequent layers. DenseNets have several compelling advantages: they alleviate the vanishing-gradient problem, encourage feature reuse and substantially improve parameter efficiency. We evaluate our proposed architecture on four highly competitive object recognition benchmark tasks (CIFAR-10, CIFAR-100, SVHN, and ImageNet). DenseNets obtain significant improvements over the state-of-the-art on most of them, whilst requiring less parameters and computation to achieve high performance. [ABSTRACT FROM AUTHOR]

The nine papers in this special section focus on new developments in agile software and reports on applications for its use. A key aspect for the extensive use of agile software is that it supports developers with coping with the growing uncertainty and turbulence in technological and market environments. Feedback and change are at the core of Agile for a dynamic, evolving, and organic, rather than static, predefined, and mechanistic development process advocated by waterfall management. To create timely, high-quality, cost-efficient, and innovative solutions, Agile developers organized in small, colocated, autonomous teams, build and test software in rapid iterative cycles, actively involving users to gather feedback, updating the project scope, and plan "on-the-fly," using face-to-face communication as opposed to documentation. These papers contribute to the state-of-the-art of agile research by offering a rich, up-todate account of the dynamics occurring when expanding Agile into "not-just-software" contexts of the key challenges and perils related to the scaling and of the possible solutions to them. [ABSTRACT FROM AUTHOR]

Using high-level synthesis techniques, this paper proposes an adaptable high-performance streaming dataflow engine for sparse matrix dense vector multiplication (SpMV) suitable for embedded FPGAs. As the SpMV is a memory-bound algorithm, this engine combines the three concepts of loop pipelining, dataflow graph, and data streaming to utilize most of the memory bandwidth available to the FPGA. The main goal of this paper is to show that FPGAs can provide comparable performance for memory-bound applications to that of the corresponding CPUs and GPUs but with significantly less energy consumption. The experimental results indicate that the FPGA provides higher performance compared to that of embedded GPUs for small and medium-size matrices by an average factor of 3.25 whereas the embedded GPU is faster for larger size matrices by an average factor of 1.58. In addition, the FPGA implementation is more energy efficient for the range of considered matrices by an average factor of 8.9 compared to the embedded CPU and GPU. A case study based on adapting the proposed SpMV optimization to accelerate the support vector machine (SVM) algorithm, one of the successful classification techniques in the machine learning literature, justifies the benefits of utilizing the proposed FPGA-based SpMV compared to that of the embedded CPU and GPU. The experimental results show that the FPGA is faster by an average factor of 1.7 and consumes less energy by an average factor of 6.8 compared to the GPU. [ABSTRACT FROM AUTHOR]

This paper analyzes security problems of modern computer systems caused by vulnerabilities in their operating systems (OSs). Our scrutiny of widely used enterprise OSs focuses on their vulnerabilities by examining the statistical data available on how vulnerabilities in these systems are disclosed and eliminated, and by assessing their criticality. This is done by using statistics from both the National Vulnerabilities Database and the Common Vulnerabilities and Exposures System. The specific technical areas the paper covers are the quantitative assessment of forever-day vulnerabilities, estimation of days-of-grey-risk, the analysis of the vulnerabilities severity and their distributions by attack vector and impact on security properties. In addition, the study aims to explore those vulnerabilities that have been found across a diverse range of OSs. This leads us to analyzing how different intrusion-tolerant architectures deploying the OS diversity impact availability, integrity, and confidentiality. [ABSTRACT FROM AUTHOR]

Heterogeneous multiprocessor systems on a chips (MPSoCs) consisting of cores with different performance/power characteristics are widely used in many real-time embedded systems, where both soft-error reliability and lifetime reliability are key concerns. Although existing efforts have investigated related problems, they either focus on one of the two reliability concerns or propose time-consuming scheduling algorithms that cannot adequately address runtime workload and environmental variations. This paper introduces an online framework which is adaptive to runtime variations and maximizes soft-error reliability while satisfying the lifetime reliability constraint for soft real-time systems executing on MPSoCs that are composed of high-performance cores and low-power (LP) cores. Based on each core’s executing frequency and utilization, the framework performs workload migration between high-performance cores and LP cores to reduce power consumption and improve soft-error reliability. Experimental results based on different hardware platforms show that the proposed approach reduces the probability of failures due to soft errors by at least 17% and 50% on average compared to a number of representative existing approaches that satisfy the same lifetime reliability constraints. [ABSTRACT FROM AUTHOR]

In high-throughput drug screening applications, as manual drug sample delivery is time-consuming and error-prone, there is an urgent need for accurate and efficient drug sample delivery biochip for large-scale microwell arrays. This paper proposes a new microfluidic biochip architecture, where drugs are automatically prepared with different concentration values, and then delivered into multiple microwells. For large-scale drug sample delivery biochips, the routing of drug sample delivery channels is a very challenging task without effective routing solutions. This paper proposes an ultrafast rule-based escape routing method, called URBER, to address the large-scale routing of drug sample delivery channels, which scales well in both runtime and memory even for a very large problem size. URBER runs very fast because it routes channels based on a set of predefined rules, which avoids runtime consumed in solution space exploration. All benchmarks for 30 ${\le }~{N}$ , ${M} {\le }~100$ have been tested, where ${N}$ and ${M}$ are the number of columns and rows of the terminal array. Among these benchmarks, about ~91.9% are routed with optimal solutions, and the runtime is order of magnitudes faster than optimal min-cost flow-based methods (speedup is from ~600 to ~340 k). Specifically, for all benchmarks with (${M}/{N}$) ${\in }$ ((3/4), (4/3)), optimal routing solutions are always obtained. URBER also shows promise of routing large-scale designs with up to 500 k terminals efficiently. [ABSTRACT FROM AUTHOR]

While the initial aim of smart meters is to provide energy readings for billing purposes, the availability of these measurements could open new opportunities for the management of future distribution grids. This paper presents a multilevel state estimator that exploits the smart meter measurements for monitoring both low and medium voltage grids. The goal of this paper is to present an architecture that is able to efficiently integrate smart meter measurements and to show the accuracy performance achievable if the use of real-time smart meter measurements for state estimation purposes was enabled. The design of the state estimator applies the uncertainty propagation theory for the integration of the data at different hierarchical levels. The coordination of the estimation levels is realized through a cloud-based infrastructure, which also provides the interface to auxiliary functions and the access to the estimation results for other distribution grid management applications. A mathematical analysis is performed to characterize the estimation algorithm in terms of accuracy and to show the performance achievable at different levels of the distribution grid when using the smart meter data. Simulations are presented, which validate the analytical results and demonstrate the operation of the multilevel estimator in coordination with the cloud-based platform. [ABSTRACT FROM AUTHOR]