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This paper presents a high-precision bandgap voltage reference (BGR) with high-order temperature compensation. The compensation signal is generated by using both strong-inversion MOSFETs and Bipolar Junction transistors (BJTs), which cancels the high-order nonlinear term $T\ln (T)$ in the BJT base-emitter voltage (VBE), and thus a low temperature coefficient (TC) over a wide temperature range is achieved. The proposed BGR circuit is fabricated in a 0.18- $\mu \text{m}$ CMOS process with an active area of $0.256 m{m^{2}}$ and a max power consumption of 1.35 mW. A minimum TC of 0.706 ${\mathrm{ppm}}/{}^ \circ C$ from $- 25\,\,{}^ \circ C$ to 125 ${}^ \circ C$ is achieved after an 8-bit resistance trimming. The line sensitivity is 0.0146%/V operating from 3.2 V to 3.7 V. The BGR achieves a power supply rejection (PSR) of −63.4 dB and a noise spectrum density of $0.92 ~\mu \text{V}/\sqrt {Hz} $ at 10 Hz. [ABSTRACT FROM AUTHOR]

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the $\text{V}_{\mathrm {OUT}}$ error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2- $\mu \text{V}$ /mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns. [ABSTRACT FROM AUTHOR]

This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with $0.18\mu m$ CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the demodulator is able to demodulate the cycle-by-cycle modulated FSK signals with low modulation index of 2.5%, with a BER of $1.24\times 10^{-5}$. [ABSTRACT FROM AUTHOR]

This paper presents a fully differential wake-up receiver (WuRX) with ultra-low power and high sensitivity. Implementing the fully differential framework achieves differential signal processing without an off-chip balun, which achieves noise suppression and sensitivity improvement. The low voltage baseband signal processing (LVBSP) is proposed to cut down the power consumption, which is achieved by the low-voltage fast-response differential amplifier (LFDA) and the time-domain signal processing circuit. Moreover, the periodic offset cancellation technique (POCT) in the baseband circuit is proposed to alleviate the offset and low-frequency noise impacts. This WuRX is implemented in the TSMC 65-nm CMOS process occupying an active area of 0.18 mm2. When operating at 434 MHz, the proposed WuRX has a −75-dBm sensitivity at 250 bps while consuming 6.4 nW from 0.4 V supply voltage. [ABSTRACT FROM AUTHOR]

Although spin orbit torque magnetic random access memory (SOT-MRAM) is one of the strong candidates for next-generation embedded memories, the degradation of read margin due to low tunnel magnetoresistance ratio (TMR) with process variations has been a large concern. In this paper, we present the dual-domain dynamic reference (DDDR) sensing scheme, where the reference voltage can be dynamically changed based on the combined voltage and time domain sensing to increase the sensing margin. The Half Schmitt trigger and sample & hold circuits are efficiently employed to generate data-dependent reference voltages and to store the sampled voltage levels at different times, respectively. According to the simulations using 28nm CMOS technology with 128 by 128 SOT-MRAM array, the proposed DDDR approach achieves a 243mV of sensing margin under 6.08E-8 bit-error-rate (BER) at 1.76ns, which is 2X larger margin with more than 100 times lower BER compared to the conventional read scheme. When scaling down the pre-charge voltage, the proposed scheme achieves more than 50% of the read energy savings under 1E-5 target BER condition. [ABSTRACT FROM AUTHOR]

In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined into a 10-bit hybrid ADC. In the first stage MDAC, a low-power push-pull amplifier is used to improve settling speed, and 1-bit redundancy is designed for calibration and dither injection. The TD-ADC with selective time domain quantization is implemented by a constant-current voltage to time converter (VTC) array and a direct positive feedback time domain comparator. The proposed VTC array can maintain high linearity with a large input swing in high-speed application. The prototype ADC was fabricated in a 28-nm CMOS process and occupied a core area of 0.074 mm2. Under a 0.95-V power supply, the chip achieves a measured peak SNDR of 53.2 dB and SFDR of 61.7 dB respectively at conversion rate up to 2.5 GS/s. The FOM is 48.2 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a $0.18 \mu \text{m}$ standard CMOS process, which occupies a chip core area of about 1.0 mm $\times0.9$ mm. It achieves >60% efficiency in the range of TEG open-circuit voltage $V_{S}$ from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the $V_{S}$ as low as 10 mV can be achieved. [ABSTRACT FROM AUTHOR]

Millimeter-wave (mmWave) RF and analog front-end circuits are very susceptible to chip process and temperature variation, which cause I/Q mismatch and DC offset. As a consequence, the system performance can be seriously degraded, especially in wideband multi-Gb/s systems. This paper proposes an online estimation and compensation in the baseband receiver end of a single carrier (SC) system for TX and RX frequency independent (FI) initial and time-varying (TV) I/Q mismatch and DC-offset. Based on specification of IEEE 802.11ay, the compensated image rejection ratio (IRR) performance of the TX and RX FI I/Q mismatch effects can be improved from 16.43 dB to 54.70 dB at SNR of 25.52 dB. Moreover, we propose a novel algorithm based on the Golay sequence for estimation and compensation to cancel TX and RX initial/TV DC-offset. The DC-offset in the I/Q channel is improved from −56.46 dB/−58.56 dB to −97.30 dB/−98.70 dB at SNR of 25.52 dB. In the hardware implementation, a four-time parallelism architecture are proposed to work at a 625 MHz clock rate with a 28-nm HPC_PLUS CMOS process under 64-QAM mode for 15 Gbps transmission. Using a clock gating control scheme for FI I/Q mismatch and DC-offset estimator, the total power of the proposed the module can be reduced from 59.5 mW to 32.7 mW. The gate count and power of the proposed estimation/compensation design are only 2.94% and 1.69% of the overall digital RX baseband gate count and power consumption. [ABSTRACT FROM AUTHOR]

Power consumption is an important limitation in designing analog-to-digital converters (ADCs) used in low-power sensing applications. This paper estimates analytically the power bound of a two-step multi-stage noise-shaping successive-approximation-register incremental ADC (two-step MASH NS-SAR IADC) proposed in our previous work. Our model considers the impacts of thermal noise, mismatch, and CMOS process (minimum feature size in CMOS technologies) on the power bounds of the proposed IADC. The analytic results show that thermal noise and CMOS process requirements determine the power consumption lower bounds in high and low resolutions, respectively. A comparison with the most competitive single-loop delta-sigma (ΔΣ) IADC shows a 3-dB higher theoretical figure-of-merit (FoM) for our proposed IADC when the resolutions are higher than 12-bit. Our proposed systematic analysis can be used to estimate the power bounds of amplifier-based NS-SAR ADCs used in either ΔΣ or incremental mode with multi-stage and multi-step topologies designed in various CMOS technologies. The reported analytic results are confirmed by experimental results of previously reported implementations. [ABSTRACT FROM AUTHOR]

This paper presents a new technique of radio frequency (RF) signal strength detection with a received signal strength indicator (RSSI) circuit which can be deployed in an internet-of-things (IoT) network. The proposed RSSI circuit is based on a direct conversion of RF to digital code indicating the signal strength. The direct conversion is achieved by the repeated switching of a rectifier’s output voltage using an ultra-low power comparator. A 5-bit programmable feedback circuit is used to correct detection inaccuracies. The RSSI circuit is implemented in a 65-nm CMOS process and consumes 6nW power. It has a linear dynamic range of 26dB and exhibits an error of ± 0.5dB with a wide bandwidth of 750MHz. A detailed analysis of the RSSI circuit is presented and verified with simulation and measurement results. The high detection accuracy with ultra-low power consumption of our RSSI circuit is favourable for IoT applications including localization, beamforming, hardware security and other low-power applications. [ABSTRACT FROM AUTHOR]

This paper proposes CMOS synapse and neuron for use in spiking neural networks to perform cognitive functions in a bio-inspired manner. The proposed synapse can trace the eligibility of the timing relationship between pre- and post-synaptic spikes, supporting a bio-plausible local learning rule called the spike timing-dependent plasticity (STDP) in an energy- and area-efficient manner. The proposed neuron can support neural functions such as synaptic current integration, threshold-based firing, neuronal leaking, membrane potential resetting, and adjustable refractory period with improved energy and area efficiency. The STDP curve shape of the synapse and the firing rate of the neuron can be adjusted as desired. Their variability due to process, voltage, and temperature (PVT) variations can also be minimized. The proposed CMOS neuron and synapse circuits were designed in a 28-nm CMOS process. The performance evaluation results indicate that the proposed synapse reduces energy consumption and area by up to 94% and 43% compared to conventional CMOS synapses. They also indicate that the proposed neuron achieves energy and area reductions of 37% and 23%, respectively, compared to conventional CMOS neurons. An associative neural network composed of the proposed neuron and synapse was designed to verify that they together work well for performing a cognitive function of associative learning and inferencing. [ABSTRACT FROM AUTHOR]

This paper presents an analog front-end (AFE) circuit with marked timing point for pulsed time-of-flight LiDAR that employs either sampling- or event-based timing approach. The proposed AFE adopts a dual-mode structure for its pre-amplifier which can be configured as a charge-sensitive amplifier (CSA) or a gated active load-assisted TIA (GALA-TIA), depending on the intensity of input current. As a result, both the sensitivity and dynamic range (DR) of the AFE have been effectively improved. In addition, the zero-crossing point of the output signal has been marked as the timing point with a built-in pulse shaper, which allows the back-end circuits of LiDAR receiver discriminate the timing conveniently and accurately. The measured input-referred RMS noise current of the proposed AFE is 37 nA. With dual-mode control, a linear output DR of 80 dB and a wide timing DR of 96 dB with walk error no more than ±160 ps have been achieved. For single-shot measurement application, only CSA mode was enabled and the pulse widths of saturated output signals have been measured to compensate the walk errors, which realized a timing DR of 78 dB with accuracy of ±150 ps. The averaged power consumption is 66 mW and the total silicon area is $0.79\times 0.42\,\,mm^{2}$ in 0.18- $\mu \text{m}$ CMOS process. [ABSTRACT FROM AUTHOR]

A novel switching-linear hybrid dynamic regulator architecture with dual-supply low dropout regulators (LDOs) is presented in this paper. This architecture leverages the intrinsic dual supplies to extend the operating range of the LDOs. Furthermore, it increases the thermo-optic tuning efficiency by reducing the LDO dropout voltage through dynamic supply modulation. This architecture is suitable for large-scale thermo-optic tuning in silicon photonics. The efficiency improvement is particularly effective when tracking signals of several adjacent channels are close to each other, e.g., wavelength tuning of a microring array. The principle of this architecture is general and can be implemented using different switching converters and LDOs. A specific design with extensive post-layout simulation results is used to verify the effectiveness of our architecture. Implemented in a 130 nm CMOS process, this design can simultaneously regulate eight output channels with an output swing of 0.8 $\text V_{\text {pp}}$. Its peak efficiency when driving 100 $\Omega $ loads is 92% at 1 V output, and the dynamic efficiency is around 86% when tracking 50 kHz sinusoidal signals. To the best of our knowledge, this is the first time that dynamic supply modulation has been applied to multi-channel thermo-optic tuning of silicon photonic devices. [ABSTRACT FROM AUTHOR]

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18- $\mu \text{m}$ partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant- $g_{m}$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/°C, and a variability $(\sigma /\mu)$ of 1.66 %. Then, two 4T+1R $\mu \text{A}$ -range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09- $\mu \text{A}$ (resp. 0.99- $\mu \text{A}$) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/°C (resp. 290-ppm/°C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma /\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations. [ABSTRACT FROM AUTHOR]

Varactors in RF CMOS processes often have significantly lower Q- factor ($Q_{VAR}$) than inductors and transformers at mm-wave frequencies. Direct connection of varactors to the outputs of an LC oscillator lowers overall tank Q, $Q_{T} < Q_{VAR}$ , and at the same time, increases the ratio of parasitic capacitance to total tank capacitance which limits frequency tuning range (FTR). Instead, magnetically coupling a varactor to the oscillator core using an asymmetric transformer, where the core is connected to the primary and varactor to the secondary, limits the drop in $Q_{T}$. The ratio of parasitic capacitance to total tank capacitance is also reduced. The varactor can also be operated in accumulation-mode, with a larger $Q_{VAR}$. Thus, both FTR and phase noise (PN), in comparison to traditional tanks in LC VCOs, are improved simultaneously. In this paper, two VCO prototypes are implemented in 65-nm CMOS. A 60 GHz self-mixing VCO with a VCO core operating at 20 GHz shows an FTR of 18.5%, a PN of −92.5 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −187.1 dBc/Hz. A 25 GHz VCO shows an FTR of 29.9%, a PN of −107.9 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −194.2 dBc/Hz. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNNs), which are inspired by the human brain, have recently gained popularity due to their relatively simple and low-power hardware for transmitting binary spikes and highly sparse activation maps. However, because SNNs contain extra time dimension information, the SNN accelerator will require more buffers and take longer to infer, especially for the more difficult high-resolution object detection task. As a result, this paper proposes a sparse compressed spiking neural network accelerator that takes advantage of the high sparsity of activation maps and weights by utilizing the proposed gated one-to-all product for low power and highly parallel model execution. The experimental result of the neural network shows 71.5% mAP with mixed (1,3) time steps on the IVS 3cls dataset. The accelerator with the TSMC 28nm CMOS process can achieve $1024\times 576.29$ frames per second processing when running at 500MHz with 35.88TOPS/W energy efficiency and 1.05mJ energy consumption per frame. [ABSTRACT FROM AUTHOR]

This paper presents a 46 nF/10 $\text{M}\Omega $ -range, digital-intensive, reconfigurable RC-to-digital converter (R2CDC) that can readout multiple C and R sensors in a time-interleaved fashion. Ratio-metric conversion using swing-boosted period-modulation (SB-PM) front-end by the R2CDC results in 114 aFrms/ $0.37 \Omega _{\text {rms}}$ resolutions and a worst-case temperature-drift of 64.2 ppm/°C over −40 to 125°C. Femto-farad capacitances can be sensed with a relative code-deviation less than 0.16 % even when parasitics vary 30 times the baseline. Implemented in a $0.18 ~\mu \text{m}$ standard CMOS process, the R2CDC consumes 140 $\mu \text{A}$ from a 1 V supply, occupying an active area of $0.175 ~\mu \text{m} ^{\mathrm{ 2}}$. [ABSTRACT FROM AUTHOR]

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 $\text{G}\Omega $ and 700 $\text{G}\Omega $ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz. [ABSTRACT FROM AUTHOR]

In this paper a low-power and high-performance 2nd-order complex band-pass filter in trans-impedance amplifier (TIA) configuration is presented. Thanks to the adopted topology for the passive network and active-components exceeds current solutions exhibiting a gain as high as 121.5 dB $_\Omega $ and 1.57 MHz of bandwidth centered around 1.33 MHz. The output noise is only 630 nV/ ${\sqrt {Hz}}$. Furthermore, a new fully-differential class-AB operational trans-conductance amplifier (OTA) provides the required current to drive heavy ADC loads with very fast signals while an improved common-mode feedback circuit enables ultra low current without introducing stability and avoids start-up problems. The filter has been integrated in a 90-nm complementary metal oxide semiconductor (CMOS) technology. Despite the high performance and accuracy of the transfer function the power consumption is only $400~\mu \text{A}$ from a 1.2-V power supply. [ABSTRACT FROM AUTHOR]

This paper presents a buffer-embedded noise-shaping SAR ADC, whose input buffer separates the capacitive DAC (CDAC) and the sampling capacitor (CS) at the input and output of the input buffer. This compensates for the non-linearity of the input buffer and reduces the CS value, resulting in a significant power saving in the input buffer. This buffer-embedded architecture enables the effective implementation of the following passive loop filter and enhances energy efficiency. A bootstrapping switch in the feedback CDAC is coupled to the output of the buffer, thereby avoiding a signal dependency due to the parasitic capacitance of the switch. The buffer-embedded noise-shaping SAR ADC occupies 0.08mm2 in a 65 nm CMOS process and features a parasitic input capacitor of 0.2 pF. It achieves 73.8 dB SNDR, 77 dB DR and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. Including the power consumption of the input buffer, the ADC consumes only 2.1 mW. [ABSTRACT FROM AUTHOR]

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard $0.18~\mu \text{m}$ CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes $1.53~\mu \text{W}$ with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling. [ABSTRACT FROM AUTHOR]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

This paper presents a novel Look-up Table (LUT) calibration technique for static non-linearity compensation in analog-to-digital converters (ADCs) with digital redundancy, such as Successive Approximation Register (SAR), Algorithmic, Sub-ranging or Pipeline ADCs. The method compensates the performance limitations of the conventional LUT approach in presence of comparison noise and/or non-monotonicity. In these circumstances, the input-output transfer function of a redundant ADC becomes significantly multivalued - that is, different output codes can be achieved for the same input level at different time instants. This behavior is motivated because from sample to sample, in a design with redundancy, the processing signal path is not unique, causing that the error under calibration becomes time-dependent, something which is not contemplated in the conventional calibration model. To deal with this effect, this work proposes a digital low-cost post-processing of the standardized Integral-Non-linearity (INL), which resolves multivalued situations using a direct access to the internal redundant codes. The method improvements are validated by realistic SAR and Pipeline ADC case studies at behavioral level, and by experimental data from an 11-bit 60Msps Pipeline ADC implemented in a 130nm CMOS process. These experimental results show that the proposed calibration achieves an improvement of approximately 1.6 effective bits at full-scale input amplitude. [ABSTRACT FROM AUTHOR]

In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing. A dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell. The TD-SRAM bitcell consisting of a 6T DESI based TD cell and a 6T-SRAM cell supports binary DNNs. In the IMC mode, 60 columns work in parallel and 96-input binary-MAC operations are processed in each column. Implemented in a standard 40-nm CMOS process, the TD-SRAM achieves the high energy efficiency of 537 TOPS/W at 0.9-V supply. With different DNN topologies, the test chips achieve the accuracy of 95.90%–98.00% with a dual 2-bit time-to-digital converter (TDC) in the MNIST dataset. [ABSTRACT FROM AUTHOR]

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, including on-chip reference buffers. [ABSTRACT FROM AUTHOR]

The continuous-time pipeline (CTP) analog-to-digital converter is an emerging technique that combines the benefits of pipelining with continuous-time operation. Prior-art multistage CTP ADCs have employed stages with identical transfer functions. This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline. We investigate the benefits of this approach when compared with conventional techniques. We also demonstrate that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter. This is accomplished by clocking the back-end ADC at a lower rate, and by appropriately modifying the digital reconstruction filters. The implicit-decimation theory is supported with measurement results from a three-stage CTP designed in a 65nm CMOS process. The converter achieves 70.4dB SNDR in a 100MHz bandwidth with its front-end operating at $f_{s}\,{=}\,800$ MHz, while the back-end samples at $f_{s}/2$. [ABSTRACT FROM AUTHOR]

A wideband CMOS low-noise amplifier (LNA) with multiple resonant frequencies is demonstrated in this article. A common source (CS) with inductive degeneration topology is widely employed in LNA circuit design to decouple the input impedance from the noise figure (NF). Since CS with inductive degeneration topology only achieves a single resonant frequency, it generally has narrow bandwidth performance. Through impedance transformation analysis of the matching circuit, a shunt resonator combined with inductive degeneration topology employed for input impedance transformation is carefully constructed to form multiple resonant frequencies. By placing resonant frequencies further apart from each other, impedance fluctuations within a wideband frequency range can be alleviated. In addition, the noise performance of this topology is the same as that of a conventional CS source-degenerated structure. The proposed LNA for the whole K/Ka Band is implemented in a commercial 65-nm CMOS process. It occupies 0.28 mm2. Under a 1.0 V voltage supply, the LNA achieves 3-dB gain bandwidth of 28 GHz from 16.5 GHz to 44.5 GHz. Within the whole 3-dB bandwidth, the gain is larger than 15.5 dB, the NF is less than 4.8 dB with a minimal value of 2.72 dB, and the input 1-dB gain compression point (IP1dB) varies from −24 dBm to −12 dBm. [ABSTRACT FROM AUTHOR]

We present an RF sampling 1 GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross-Coupled Pair (HXCP) is proposed in a $\text{G}_{\text {m}}$ -R based residue amplifier design as a critical part of the presented ADC. This technique overcomes the challenges in designing analog amplifiers using advanced nanometer CMOS processes and achieves the gain and linearity required for the ADC. By implementing the HXCP in a residue amplifier (RA), the proposed technique successfully improves the RA linearity by at least 10 dB and meanwhile boosts the gain of the RA to be about 8. The entire ADC consists of three stages each with 4-bit, 4-bit, and 6-bit, respectively. Two one-bit interstage redundancies are implemented between the three stages. Various techniques are also implemented to help the ADC achieve the targeted speed and resolution. The presented ADC was implemented in a 28nm CMOS process and achieves an ERBW of 1 GHz, an SNDR of 60.7 dB, an SFDR of 73 dB at Nyquist input (495 MHz) and an SFDR of 82 dB at 1 GHz input. A 7.5 fj/conv-step FoMw and a 169.4 dB FoMs are achieved, which demonstrate one of the best Figure of Merits (FoMs) among ADCs of similar speed and resolution. [ABSTRACT FROM AUTHOR]

A digital-intensive four-level pulse amplitude (PAM-4) transceiver featuring a 2-tap time-based decision feedback equalization (TB-DFE) circuit was demonstrated in a 65 nm GP CMOS process. A novel inverter-based differential voltage-to-time converter (DVTC) increases the linearity and dynamic range compared to a prior time-based DFE approach enabling reliable PAM-4 operation. The four-level signal comparison and DFE operation were performed entirely in the time domain using programmable delays and a phase detector (PD). Using an on-chip bit error rate (BER) monitor, we verified a BER less than 10−12 while achieving an energy-efficiency of 0.97pJ/b at a 32Gb/s data rate. The transmitter (TX) and receiver (RX) circuits occupy an area of 0.009 mm2. [ABSTRACT FROM AUTHOR]

An odd-element half-wave-rectification superposition (OHS) technique is presented and verified for designing the high-multiplication factor frequency multipliers. The proposed OHS technique superposes N odd-element phase-shifted half-wave-rectification (HWR) fundamental signals ($f_{0}$) to extract the 2N-order harmonic (2N $f_{0}$) while canceling the fundamental ($f_{0}$) and the 2nd to (2N-1)th harmonics without extra filtering. Compared with the reported even-element half-wave-rectification superposition technique (EHS) technique, the proposed OHS technique can realize the same multiplication factor but requires only a half number of the input HWR signals. Thus, the proposed OHS technique can be applied to design the high-multiplication factor frequency multiplier that is difficult to be implemented using the reported EHS technique. To verify the validity of the proposed OHS technique, a differential $\times 6$ frequency multiplier with the input frequency range of 5-7GHz and output frequency range of 30–42 GHz was implemented in 65 nm CMOS process. The experimental results indicate that the implemented $\times 6$ frequency multiplier exhibits more than 23 dBc rejection to the fundamental and 2nd to 5th harmonics without the extra filter. The DC power consumption is 4.6 mW for the core circuit. [ABSTRACT FROM AUTHOR]

A CMOS Hall-based fully integrated isolation amplifier for differential voltage sensing is presented in this work. The design is fabricated in a $0.35 \mu \text{m}$ CMOS process in which the high voltage (HV) side of the amplifier contains a coil driver while the low voltage (LV) side includes a Hall-effect sensor, low-noise amplifier, programmable-gain amplifier, filter, and chopper switches. Another Hall sensor performs the digital isolation using the on-off keying (OOK) technique for clock recovery. The introduced prototype achieves above 120 dB of isolation mode rejection (IMR) at 60 Hz and operates at a continuous isolation working voltage of 0.6 kV. It has also a maximum nonlinearity of 0.64 %, an input-referred offset of 1 mV, a 40 dB full-scale signal-to-noise ratio over a 40 kHz bandwidth, and a spurious-free dynamic range of 64 dB. The silicon area for each of the two separate dices employed for the HV and LV side of the isolation amplifier is 1 mm2 with a power consumption of 7.6 mW and 9.9 mW respectively. The achieved miniaturized size of the isolation components, as well as their significantly low-power consumption, ensure the suitability of the proposed isolation amplifier for multi-channel readout circuit applications. [ABSTRACT FROM AUTHOR]

This work presents a galvanically isolated chip-to-chip communication system that utilizes laterally coupled resonators in combination with a new differential full-wave receiver architecture. Lateral resonant coupling increases the isolation capability and significantly minimizes the intra-chip coupling capacitance of galvanic isolators beyond the limits of vertical coupling in standard CMOS. The presented system marries the merits of a laterally resonant coupled channel with a source-gate coupled low-power, low-latency RF detector architecture that enables high common-mode and differential noise immunity. A center-tapped transformer is used as the interface between the proposed fully differential receiver and the communication channel to further enhance the common-mode transient immunity (CMTI). The proposed system is integrated in a $0.25~\mu \text{m}$ CMOS process with four metal layers and does not alter the native process or necessitate additional fabrication steps. The design does not require exotic packaging and achieves state-of-art CMTI of 650 kV/ $\mu \text{s}$ at 5 kVpk isolation, sub-20ns propagation delay, and maintains a small form-factor of 0.95 mm2. The GI system exhibits robust performance to fabrication variations, with less than ±0.3% and ±8% sensitivity to process variation and post-assembly chip distance offset, respectively. [ABSTRACT FROM AUTHOR]

The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the impact of such P-Z pairs on the settling time of CMOS OTAs - using low-frequency zeros and cascaded-gain stages - consequently revealing un-tapped opportunities for many-stage CMOS OTA design. The proposed theory will be validated and verified through a design example that also demonstrates how the generalized theory unveils opportunities for many-stage OTA design. The presented example is a 2- to 8-stage CMOS OTA based on the TSMC 65 nm CMOS process, verified through simulations (schematic and post-layout) as well as some measurement results. [ABSTRACT FROM AUTHOR]

With the development of the Internet of things (IoT), sensors are being mounted on various objects. This trend has prompted demand for low-power, high-performance information processing on the edge side. Here, an Ising model architecture that can efficiently solve optimization problems would be an efficient processing solution for edges. In this study, we implemented a 512- spin fully connected Ising model on an LSI chip fabricated in a 28-nm CMOS process. The fully connected Ising model was implemented in the chip by using pseudo-annealing (PA), which is easier to implement than simulated annealing (SA). In addition, we devised a multi-spin-thread structure, concurrent update structure, and a folded interaction placement for accuracy, speed, and compactness. Because eight spin threads are implemented, the calculation throughput could be increased by a factor of eight in comparison with a single spin-thread implementation. Moreover, as a measure of solution accuracy, the average route length of a 22-city traveling salesman problem was reduced by 19% and the standard deviation (SD) was reduced by 46%. Likewise, the average cut value of a 512- node max-cut problem was increased by 1.6% and SD was decreased by 60%. The concurrent update almost doubled the calculation speed in comparison with the case of no concurrent update. In addition, the circuit area was reduced by about 38% as a result of the folded interaction placement. The time required to obtain a solution was 128 ms. The chip at annealing processing (main processing) had a power consumption of 12 mW at 1 MHz. [ABSTRACT FROM AUTHOR]

This article presents a highly-efficient radio frequency energy harvester that utilizes an extra matching network to produce a passively-amplified adaptive compensation voltage. The compensation voltage produced on the gate of the transistors reduces the transistors’ conduction loss by increasing the gate-source voltage when transistors are on and reduces the leakage current by producing a negative gate-source voltage when the transistors are off. This is the first work that produces an adaptive compensation voltage without using active components, resulting in a significantly higher conversion efficiency if passive components of high quality are utilized. The mathematical derivations show that the forward conduction loss and the leakage current of the transistors are minimized by utilizing the proposed technique, increasing the overall efficiency. The proposed rectifier is fabricated in a TSMC 130 nm standard CMOS process, and measurement results and simulation results are in good agreement. Measurement results show that the rectifier achieves the maximum efficiency of 61% and 63.4% for battery load of 1.2 V and 1.5 V, respectively, which is at least 20 % larger than the efficiency of the conventional Dickson’s rectifiers. [ABSTRACT FROM AUTHOR]

Charge balancing has become a common key safety requirement of electrical stimulation systems. It reduces the risk of electrode dissolution and tissue damage, which might arise after unbalanced stimulation pulses. A CMOS integrated consequence-based active charge balancer is presented that instantaneously removes excess charges between two consecutive stimulation pulses. This balancer provides a highly adaptive power supply compliance from 3.3 V to 38 V, verified by measurements. In order to maintain the compensation behavior and efficacy over the entire supply range and to protect the active components at such high voltages, a quad-rail design is elaborated that overcomes the technological high voltage limitations of the employed 0.35 $\mu \text{m}$ CMOS process. The presented charge balancing circuit consists of a fully differential operational transconductance amplifier for monitoring and voltage level translation, as well as an advanced class-B stage as current driver, designed in accordance with the quad-rail concept. Further system flexibility is provided by incorporating three different compensation current limitations of $\pm 500~\mu \text{A}$ , $\pm 300~\mu \text{A}$ and $\pm 200~\mu \text{A}$. Additionally, two safety limits of ±50 mV and ±100 mV have been adopted. The charge balancer is very power efficient, it only dissipates 6.3 $\mu \text{W}$ and 25 $\mu \text{W}$ , at 3.3 V and 38 V respectively. [ABSTRACT FROM AUTHOR]

Stereo vision is widely deployed on robots and drones to enable depth estimation at a low cost. The combination of lightweight deep neural network (DNN) and cost volumes algorithm is proved to possess the advantages of both high depth estimation accuracy and speed. However, currently there is no accelerator architecture compatible with both efficient DNN inference and cost generation algorithms such as stereo matching. This work proposes a stereo vision accelerator called Dadu-eye, dedicated to real-time processing of high-resolution image streams. The proposed architecture adopts a pipelined hardware design with the techniques of operation approximation and scheduling-level optimization. First, a cost estimation block is designed to generate cost volumes from both luminance and color information. Second, a super pipelined multiplication and accumulation array with a row scan-based fused-layer convolution scheduling is proposed to perform the encoding and decoding neural network efficiently. Finally, an optical flow block is designed and cooperates with the array to approximately predict half of the frames’ depth to achieve real-time (30fps) processing on 1080p view. Based on the SMIC 40 nm CMOS process, this stereo vision accelerator achieves 5.3 TOPS/W power efficiency and significantly reduces 81% off-chip memory access. [ABSTRACT FROM AUTHOR]

In this work, the design methodology of the relaxation oscillator with the post-processing trimming option for frequency and temperature coefficient is presented. A novel oscillator core is introduced, which ensures good control linearity and insensitivity to CMOS variations of the output frequency as a prerequisite for frequency and temperature calibration. The proposed oscillator operates at 2 MHz and consumes typically about $I_{DD}=97.8\,\,\mu \text{A}$ at the nominal temperature of 42.5°C and nominal supply voltage of $V_{DD}=1.8$ V. The oscillator is verified experimentally with 10 samples manufactured in 180 nm CMOS process, each covering an area of 0.075 mm2. The frequency and temperature calibration was performed based on the two-point temperature measurements, resulting in a significant improvement in frequency stability. The temperature calibrated oscillator has a temperature variation ±0.30% in the temperature range from −40°C to 125°C, and the variation with the power supply ±0.07% in the supply range from 1.62 V to 1.98 V. [ABSTRACT FROM AUTHOR]