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Aggregating features in terms of different convolutional blocks or contextual embeddings has been proven to be an effective way to strengthen feature representations for semantic segmentation. However, most of the current popular network architectures tend to ignore the misalignment issues during the feature aggregation process caused by step-by-step downsampling operations and indiscriminate contextual information fusion. In this paper, we explore the principles in addressing such feature misalignment issues and inventively propose Feature-Aligned Segmentation Networks (AlignSeg). AlignSeg consists of two primary modules, i.e., the Aligned Feature Aggregation (AlignFA) module and the Aligned Context Modeling (AlignCM) module. First, AlignFA adopts a simple learnable interpolation strategy to learn transformation offsets of pixels, which can effectively relieve the feature misalignment issue caused by multi-resolution feature aggregation. Second, with the contextual embeddings in hand, AlignCM enables each pixel to choose private custom contextual information adaptively, making the contextual embeddings be better aligned. We validate the effectiveness of our AlignSeg network with extensive experiments on Cityscapes and ADE20K, achieving new state-of-the-art mIoU scores of 82.6 and 45.95 percent, respectively. Our source code is available at https://github.com/speedinghzl/AlignSeg. [ABSTRACT FROM AUTHOR]

Grid connected inverter controllers require the magnitude and phase of the point of common coupling voltage for the generation of unit vectors from a phase locked loop. However, weak grid conditions or grid voltage sensor failures might substantially increase control difficulty in the inverter due to unknown grid impedance which causes instability in the phase locked loop. In this paper, an internal model based grid voltage estimation architecture has been presented. The proposed control architecture relies on the current measurements along with nominal values of filter parameters for the point of common coupling voltage estimation and unit vector generation. Detailed stiffness and robustness analyses are presented to show that the proposed control and estimation architecture is nearly insensitive to parameter variations. In comparison to conventional current control with both voltage and current sensors, the proposed current control scheme provides better transient response during both ideal and non-ideal grid voltage conditions. Experimental results on a reduced scale laboratory prototype validate the efficacy of the proposed architecture. [ABSTRACT FROM AUTHOR]

Due to the fact that most user equipments (UEs) do not have enough computation power, time-sensitive tasks should be offloaded to other computation resources. In such cases, a cloud is an ideal destination to which computation tasks can be offloaded because of its huge data processing power. However, the distance between a UE and the cloud may increase the latency of data transmission. At the same time, edges and vehicular-fogs (consisting of electric vehicles with computing resources) are closer to UEs and mostly remain under-utilized. To address this issue, a federated architecture with UEs, vehicular-fogs (parking lot fog and traffic intersection fog), edges, and cloud is proposed along with a probabilistic offloading strategy. The quality of service (QoS) violation probability can be minimized by finding the optimal offloading probabilities while satisfying the delay constraint through an optimal offloading probability estimation algorithm based on the subgradient method proposed in this paper. Our results show that the QoS violation probability and the average waiting time can be decreased by 10%-12% and 45%, respectively, for a federated architecture with two vehicular-fogs as compared to an architecture without any fogs. As offloading to edges and cloud has longer communication delays than offloading to vehicular-fogs, the offloading probabilities to the edges in the architecture with two vehicular-fogs in the case of heavy traffic are reduced by nearly 35% as compared to the architecture without any fogs. [ABSTRACT FROM AUTHOR]

The papers in this special section explore cutting edge research on topics that combine artificial intelligence with edge computing, relating to the design, performance, or application of microprocessors and microcomputers. [ABSTRACT FROM AUTHOR]

The performance of a single neural network can vary unexpectedly corresponding to different classification tasks, and thus the network with fixed structure may lack flexibility and often lead to overfitting or underfitting. It is urgent, also the main objective of this paper, to deal with the limitation of the fixed neural network structure on classifying radar signals in different electromagnetic environments. We in this paper propose a variable network architecture search (NAS) mechanism, called balanced-NAS framework, and apply it in specific emitter identification (SEI) to greatly improve the flexibility of model searching. In the proposed balanced-NAS framework, a “block-cell” structure and a controller based recurrent neural network (RNN) are utilized to design models automatically according to external environment. In particular, a balance function is also proposed and utilized in the balanced-NAS framework, acting on the RNN controller to take both the validation accuracy and computational budget into consideration while searching for ideal models. The efficiency of the searching process is further enhanced by exploiting a progressive strategy to design simple and complicate child models where unpromising ones after each evaluation process are obsoleted to release searching space. Simulations and experiments indicate that the proposed balanced-NAS framework is extremely efficient and outperforms the conventional algorithms in classifying radar signals in different environments. [ABSTRACT FROM AUTHOR]

This paper deals with adaptive radar detection problems where several alternative hypotheses may be plausible. This kind of problems naturally extends the conventional binary tests that often occur in radar (as well as in other application fields) by including a further uncertainty degree related to the number of unknown signal parameters (model order). Such a modification consequently leads to multiple composite alternative hypotheses. In the companion paper (Addabbo et al., 2021), we have defined a new design framework which allows us to come up with decision schemes for these hypothesis testing problems by exploiting the Kullback-Leibler Information Criterion and without resorting to heuristic design criteria. The architectures devised within the proposed framework consist of the sum between the compressed log-likelihood ratio and a penalty term inherited from model order selection rules. Such a penalty term accounts for the number of unknown parameters to overcome the limitation of the generalized likelihood ratio test in the presence of nested hypotheses. In the present paper, we apply the new design framework to different detection problems related to both real aperture and (polarimetric) synthetic aperture radar. The analysis is carried out in comparison with suitable competitors (possibly based upon heuristic design criteria) and shows that the architectures devised within the proposed theoretically-founded design framework represent an effective means to deal with detection problems where the uncertainty on some parameters leads to multiple alternative hypotheses. [ABSTRACT FROM AUTHOR]

Convolutional networks have achieved great success in various vision tasks. This is mainly due to a considerable amount of research on network structure. In this study, instead of focusing on architectures, we focused on the convolution unit itself. The existing convolution unit has a fixed shape and is limited to observing restricted receptive fields. In earlier work, we proposed the active convolution unit (ACU), which can freely define its shape and learn by itself. In this paper, we provide a detailed analysis of the previously proposed unit and show that it is an efficient representation of a sparse weight convolution. Furthermore, we extend an ACU to a grouped ACU, which can observe multiple receptive fields in one layer. We found that the performance of a naive grouped convolution is degraded by increasing the number of groups; however, the proposed unit retains the accuracy even though the number of parameters decreases. Based on this result, we suggest a depthwise ACU (DACU), and various experiments have shown that our unit is efficient and can replace the existing convolutions. [ABSTRACT FROM AUTHOR]

Augmenting neural networks with skip connections, as introduced in the so-called ResNet architecture, surprised the community by enabling the training of networks of more than 1,000 layers with significant performance gains. This paper deciphers ResNet by analyzing the effect of skip connections, and puts forward new theoretical results on the advantages of identity skip connections in neural networks. We prove that the skip connections in the residual blocks facilitate preserving the norm of the gradient, and lead to stable back-propagation, which is desirable from optimization perspective. We also show that, perhaps surprisingly, as more residual blocks are stacked, the norm-preservation of the network is enhanced. Our theoretical arguments are supported by extensive empirical evidence. Can we push for extra norm-preservation? We answer this question by proposing an efficient method to regularize the singular values of the convolution operator and making the ResNet’s transition layers extra norm-preserving. Our numerical investigations demonstrate that the learning dynamics and the classification performance of ResNet can be improved by making it even more norm preserving. Our results and the introduced modification for ResNet, referred to as Procrustes ResNets, can be used as a guide for training deeper networks and can also inspire new deeper architectures. [ABSTRACT FROM AUTHOR]

With the rapid development of connecting massive devices to the Internet, especially for remote areas without cellular network infrastructures, space-air-ground integrated networks (SAGINs) emerge and offload computation-intensive tasks. In this paper, we consider a SAGIN, where multiple low-earth-orbit (LEO) satellites providing connections to the cloud server, an unmanned aerial vehicle (UAV), and nearby base stations (BSs) providing edge computing services are included. The UAV flies along a fixed trajectory to collect tasks generated by Internet of Things (IoT) devices, and forwards these tasks to a BS or the cloud server for further processing. To facilitate efficient processing, the UAV needs to decide where to offload as well as the proportion of offloaded tasks. However, in practice, due to the variability of environment and actual demand, the amount of arrival tasks is uncertain. If the deterministic optimization is utilized to develop offloading strategy, unnecessary system overhead or higher task drop rate may occur, which severely damages the system robustness. To address this issue, we characterize the uncertainty with a data-driven approach, and formulate a distributionally robust optimization problem to minimize the expected energy-constrained system latency under the worst-case probability distribution. Furthermore, the distributionally robust latency optimization algorithm is proposed to reach the sub-optimal solution. Finally, we perform simulations on the real-world data set, and compare with other benchmark schemes to verify the efficiency and robustness of our proposed algorithm. [ABSTRACT FROM AUTHOR]

We are seeing a growth in the number of connected vehicles in Vehicular Ad-hoc Networks (VANETs) to achieve the goal of Intelligent Transportation System (ITS). This is leading to a connected vehicular network scenario with vehicles continuously broadcasting data to other vehicles on the road and the roadside network infrastructure. The presence of a large number of communicating vehicles greatly increases the number and types of possible anomalies in the network. Existing works provide solutions addressing specific anomalies in the network only. However, since there can be a multitude of anomalies possible in the network, there is a need for better anomaly detection frameworks that can address this unprecedented scenario. In this paper, we propose an anomaly detection framework for VANETs based on deep neural networks (DNNs) using a sequence reconstruction and thresholding algorithm. In this framework, the DNN architectures are deployed on the roadside units (RSUs) which receive the broadcast vehicular data and run anomaly detection tasks to classify a particular message sequence as anomalous or genuine. Multiple DNN architectures are implemented in this experiment and their performance is compared using key evaluation metrics. Performance comparison of the proposed framework is also drawn against the prior work in this area. Our best performing deep learning-based scheme detects anomalous sequences with an accuracy of 98%, a great improvement over the set benchmark. [ABSTRACT FROM AUTHOR]

Future wireless networks need to support massive machine type communication (mMTC) where a massive number of devices accesses the network and massive MIMO is a promising enabling technology. Massive access schemes have been studied for co-located massive MIMO arrays. In this paper, we investigate the activity detection in grant-free random access for mMTC in cell-free massive MIMO networks using distributed arrays. Each active device transmits a non-orthogonal pilot sequence to the access points (APs) and the APs send the received signals to a central processing unit (CPU) for joint activity detection. The maximum likelihood device activity detection problem is formulated and algorithms for activity detection in cell-free massive MIMO are provided to solve it. The simulation results show that the macro diversity gain provided by the cell-free architecture improves the activity detection performance compared to co-located architecture when the coverage area is large. [ABSTRACT FROM AUTHOR]

Cell-free massive multiple-input-multiple-output (mMIMO) is an emerging technology for beyond 5G with its promising features such as higher spectral efficiency and superior spatial diversity as compared to conventional multiple-input-multiple-output (MIMO) technology. The main working principle of cell-free mMIMO is that many distributed access points (APs) cooperate simultaneously to serve all the users within the network without creating cell boundaries. This paper considers the uplink of a cell-free mMIMO system utilizing the radio stripe network architecture with a sequential fronthaul between the APs. A novel uplink sequential processing algorithm is developed, which is proved to be optimal in both the maximum spectral efficiency (SE) and the minimum mean square error (MSE) sense. A detailed quantitative analysis of the fronthaul requirement or signaling of the proposed algorithm and its comparison with competing sub-optimal algorithms is provided. Key conclusions and implications are summarized in the form of corollaries. Based on the analytical and numerical simulation results, we conclude that the proposed scheme can significantly reduce the fronthaul signaling, without compromising the communication performance. [ABSTRACT FROM AUTHOR]

Neural architecture search (NAS) has emerged as a promising avenue for automatically designing task-specific neural networks. Existing NAS approaches require one complete search for each deployment specification of hardware or objective. This is a computationally impractical endeavor given the potentially large number of application scenarios. In this paper, we propose Neural Architecture Transfer (NAT) to overcome this limitation. NAT is designed to efficiently generate task-specific custom models that are competitive under multiple conflicting objectives. To realize this goal we learn task-specific supernets from which specialized subnets can be sampled without any additional training. The key to our approach is an integrated online transfer learning and many-objective evolutionary search procedure. A pre-trained supernet is iteratively adapted while simultaneously searching for task-specific subnets. We demonstrate the efficacy of NAT on 11 benchmark image classification tasks ranging from large-scale multi-class to small-scale fine-grained datasets. In all cases, including ImageNet, NATNets improve upon the state-of-the-art under mobile settings (≤ 600M Multiply-Adds). Surprisingly, small-scale fine-grained datasets benefit the most from NAT. At the same time, the architecture search and transfer is orders of magnitude more efficient than existing NAS methods. Overall, experimental evaluation indicates that, across diverse image classification tasks and computational objectives, NAT is an appreciably more effective alternative to conventional transfer learning of fine-tuning weights of an existing network architecture learned on standard datasets. Code is available at https://github.com/human-analysis/neural-architecture-transfer. [ABSTRACT FROM AUTHOR]

Safety-critical systems in various industries such as transportation or nuclear energy have been paid more attention with the development of societies due to increased attachment of importance to the life of human, their property, and nature. While developing such systems, detailed availability and safety characteristics are to be taken into account in parallel with architectural design decisions such as synchronization between different computing units or real-time task management. For fulfilling top-level requirements in international standards, ambitious quantitative targets like 0.012 FIT for HW units are to be reached where the industry has difficulties to achieve it. In this paper, this problem is handled by proposing an augmented Markov model for diverse architectures that is superior to the formulas provided in the main safety standard IEC 61508 and previous studies. With the proposed method it is possible to cover all safety-relevant states, which leads to more accuracy and lower hazard rates helping to reach these ambitious quantitative targets. Besides, the reliability parameters are investigated and optimized to increase safety performance. Consequently, the proposed novel model including enhanced reliability parameters is used for an industry application, namely safety-critical computer used for unmanned metro and high-speed rail transportation. The result obtained by the proposed model is compared with the results obtained using state of art models in literature and using the formulas in IEC 61508. As domain independent references IEC 61508 and Markovian approach are used in the paper, this study is applicable to other safety critical areas such as automotive or avionic industry. [ABSTRACT FROM AUTHOR]

To meet the execution requirements of delay-sensitive services in vehicular edge computing (VEC) networks, vehicular services need to be offloaded to edge computing nodes. For complex, large-scale services, the services need to be migrated if the services are not completed before the vehicles leave the coverage of edge computing nodes. Trust and resource matching between areas thus become major problems. This paper studies the decision model of vehicular service offloading and migration. First, software-defined network (SDN) technology is introduced into the traditional network architecture, and a two-layer distributed SDN-controlled VEC network architecture is designed, which is divided into a domain control layer and an area control layer. In this framework, we use the consortium blockchain as a carrier to share network topology information between SDN controllers to prevent information leakage. We then established a service offloading and migration optimization problem model to minimize service execution delay, reduce energy consumption and maximize the throughput of the blockchain system. We describe the problem model as a Markov Decision Process (MDP), introduce a deep reinforcement learning (DRL) algorithm named asynchronous advantage actor-critic (A3C) and design a dynamic service offloading and migration algorithm (DSOMA) based on A3C to solve the problem. Simulation results show that DSOMA can increase the throughput of the blockchain system, and DSOMA is superior to the deep Q-learning (DQN) algorithm and greedy offloading algorithm in reducing service execution delay and system energy consumption. [ABSTRACT FROM AUTHOR]

Tensor Cores have been an important unit to accelerate Fused Matrix Multiplication Accumulation (MMA) in all NVIDIA GPUs since Volta Architecture. To program Tensor Cores, users have to use either legacy wmma APIs or current mma APIs. Legacy wmma APIs are more easy-to-use but can only exploit limited features and power of Tensor Cores. Specifically, wmma APIs support fewer operand shapes and can not leverage the new sparse matrix multiplication feature of the newest Ampere Tensor Cores. However, the performance of current programming interface has not been well explored. Furthermore, the computation numeric behaviors of low-precision floating points (TF32, BF16, and FP16) supported by the newest Ampere Tensor Cores are also mysterious. In this paper, we explore the throughput and latency of current programming APIs. We also intuitively study the numeric behaviors of Tensor Cores MMA and profile the intermediate operations including multiplication, addition of inner product, and accumulation. All codes used in this work can be found in https://github.com/sunlex0717/DissectingTensorCores. [ABSTRACT FROM AUTHOR]

In recent years, remarkable progress in zero-shot learning (ZSL) has been achieved by generative adversarial networks (GAN). To compensate for the lack of training samples in ZSL, a surge of GAN architectures have been developed by human experts through trial-and-error testing. Despite their efficacy, however, there is still no guarantee that these hand-crafted models can consistently achieve good performance across diversified datasets or scenarios. Accordingly, in this paper, we turn to neural architecture search (NAS) and make the first attempt to bring NAS techniques into the ZSL realm. Specifically, we propose a differentiable GAN architecture search method over a specifically designed search space for zero-shot learning, referred to as ZeroNAS. Considering the relevance and balance of the generator and discriminator, ZeroNAS jointly searches their architectures in a min-max player game via adversarial training. Extensive experiments conducted on four widely used benchmark datasets demonstrate that ZeroNAS is capable of discovering desirable architectures that perform favorably against state-of-the-art ZSL and generalized zero-shot learning (GZSL) approaches. Source code is at https://github.com/caixiay/ZeroNAS. [ABSTRACT FROM AUTHOR]

Functional and nonfunctional characteristics of software systems are defined by their architecture. Therefore, research streams such as Internet-of-Things (IoT) or component-based software engineering provide researchers and practitioners with construction guidelines for selected architectural characteristics. Current systems can be categorized in delivering services to the user and being engineered in a smart way. For example, services being provided by IoT-Systems must fulfill users’ goals in a highly dynamic and ad-hoc way. Consequently, this survey aims at answering various research questions regarding the methodical composition of system components and services. Furthermore, new research opportunities are sketched that should be tackled to make the scientific progress available to practitioners. Based on a systematic literature review from a software architecture point of view, in this paper we identify 75 primary studies for domain-specific IoT component composition approaches and architectures. Initial results show that current integration approaches mainly focus on performance evaluation of their integration solutions, which may be too narrow for fulfilling user goals by utilizing of IoT architectures. [ABSTRACT FROM AUTHOR]

Long short-term memory (LSTM) is a type of powerful deep neural network that has been widely used in many sequence analysis and modeling applications. However, the large model size problem of LSTM networks make their practical deployment still very challenging, especially for the video recognition tasks that require high-dimensional input data. Aiming to overcome this limitation and fully unlock the potentials of LSTM models, in this paper we propose to perform algorithm and hardware co-design towards high-performance energy-efficient LSTM networks. At algorithm level, we propose to develop fully decomposed hierarchical Tucker (FDHT) structure-based LSTM, namely FDHT-LSTM, which enjoys ultra-low model complexity while still achieving high accuracy. In order to fully reap such attractive algorithmic benefit, we further develop the corresponding customized hardware architecture to support the efficient execution of the proposed FDHT-LSTM model. With the delicate design of memory access scheme, the complicated matrix transformation can be efficiently supported by the underlying hardware without any access conflict in an on-the-fly way. Our evaluation results show that both the proposed ultra-compact FDHT-LSTM models and the corresponding hardware accelerator achieve very high performance. Compared with the state-of-the-art compressed LSTM models, FDHT-LSTM enjoys both order-of-magnitude reduction (more than $1000 \times$ 1000 × ) in model size and significant accuracy improvement (0.6% to 12.7%) across different video recognition datasets. Meanwhile, compared with the state-of-the-art tensor decomposed model-oriented hardware TIE, our proposed FDHT-LSTM architecture achieve $2.5\times$ 2. 5 × , $1.46\times$ 1. 46 × and $2.41\times$ 2. 41 × increase in throughput, area efficiency and energy efficiency, respectively on LSTM-Youtube workload. For LSTM-UCF workload, our proposed design also outperforms TIE with $1.9\times$ 1. 9 × higher throughput, $1.83\times$ 1. 83 × higher energy efficiency and comparable area efficiency. [ABSTRACT FROM AUTHOR]

Parallelism and data reuse are the most critical issues for the design of hardware acceleration in a deep learning processor. Besides, abundant on-chip memories and precise data management are intrinsic design requirements because most of deep learning algorithms are data-driven and memory-bound. In this paper, we propose a compiler-architecture co-design scheme targeting a reconfigurable and algorithm-oriented array processor, named ReAAP. Given specific deep neural networks, the proposed co-design scheme is effective to perform parallelism and data reuse optimization on compute-intensive layers for guiding reconfigurable computing in hardware. Especially, the systemic optimization is performed in our proposed domain-specific compiler to deal with the intrinsic tensions between parallelism and data locality, for the purpose of automatically mapping diverse layer-level workloads onto our proposed reconfigurable array architecture. In this architecture, abundant on-chip memories are software-controlled and its massive data access is precisely handled by compiler-generated instructions. In our experiments, the ReAAP is implemented on an embedded FPGA platform. Experimental results demonstrate that our proposed co-design scheme is effective to integrate software flexibility with hardware parallelism for accelerating diverse deep learning workloads. As a whole system, ReAAP achieves a consistently high utilization of hardware resource for accelerating all the diverse compute-intensive layers in ResNet, MobileNet, and BERT. [ABSTRACT FROM AUTHOR]

Edge systems are required to autonomously make real-time decisions based on large quantities of input data under strict power, performance, area, and other constraints. Meeting these constraints is only possible by specializing systems through hardware accelerators purposefully built for machine learning and data analysis algorithms. However, data science evolves at a quick pace, and manual design of custom accelerators has high non-recurrent engineering costs: general solutions are needed to automatically and rapidly transition from the formulation of a new algorithm to the deployment of a dedicated hardware implementation. Our solution is the SOftware Defined Architectures (SODA) Synthesizer, an end-to-end, multi-level, modular, extensible compiler toolchain providing a direct path from machine learning tools to hardware. The SODA Synthesizer frontend is based on the multilevel intermediate representation (MLIR) framework; it ingests pre-trained machine learning models, identifies kernels suited for acceleration, performs high-level optimizations, and prepares them for hardware synthesis. In the backend, SODA leverages state-of-the-art high-level synthesis techniques to generate highly efficient accelerators, targeting both field programmable devices (FPGAs) and application-specific circuits (ASICs). In this paper, we describe how the SODA Synthesizer can also assemble the generated accelerators (based on the finite state machine with datapath model) in a custom system driven by a distributed controller, building a coarse-grained dataflow architecture that does not require a host processor to orchestrate parallel execution of multiple accelerators. We show the effectiveness of our approach by automatically generating ASIC accelerators for layers of popular deep neural networks (DNNs). Our high-level optimizations result in up to 74x speedup on isolated accelerators for individual DNN layers, and our dynamically scheduled architecture yields an additional 3x performance improvement when combining accelerators to handle streaming inputs. [ABSTRACT FROM AUTHOR]

Deep Neural Networks (DNN) are gaining higher commercial values in computer vision applications, e.g., image classification, video analytics, etc. This calls for urgent demands of the intellectual property (IP) protection of DNN models. In this paper, we present a novel watermarking scheme to achieve the ownership verification of DNN architectures. Existing works all embedded watermarks into the model parameters while treating the architecture as public property. These solutions were proven to be vulnerable by an adversary to detect or remove the watermarks. In contrast, we claim the model architectures as an important IP for model owners, and propose to implant watermarks into the architectures. We design new algorithms based on Neural Architecture Search (NAS) to generate watermarked architectures, which are unique enough to represent the ownership, while maintaining high model usability. Such watermarks can be extracted via side-channel-based model extraction techniques with high fidelity. We conduct comprehensive experiments on watermarked CNN models for image classification tasks and the experimental results show our scheme has negligible impact on the model performance, and exhibits strong robustness against various model transformations and adaptive attacks. [ABSTRACT FROM AUTHOR]

Training jobs of deep neural networks (DNNs) can be accelerated through distributed variants of stochastic gradient descent (SGD), where multiple nodes process training examples and exchange updates. The total throughput of the nodes depends not only on their computing power, but also on their networking speeds and coordination mechanism (synchronous or asynchronous, centralized or decentralized), since communication bottlenecks and stragglers can result in sublinear scaling when additional nodes are provisioned. In this paper, we propose two classes of performance models to predict throughput of distributed SGD: fine-grained models, representing many elementary computation/communication operations and their dependencies; and coarse-grained models, where SGD steps at each node are represented as a sequence of high-level phases without parallelism between computation and communication. Using a PyTorch implementation, real-world DNN models and different cloud environments, our experimental evaluation illustrates that, while fine-grained models are more accurate and can be easily adapted to new variants of distributed SGD, coarse-grained models can provide similarly accurate predictions when augmented with ad hoc heuristics, and their parameters can be estimated with profiling information that is easier to collect. [ABSTRACT FROM AUTHOR]

In this paper, we build a $TC$ T C - $Stream$ S t r e a m , a high-performance graph processing system specific for a triangle counting algorithm on graph data with up to tens of billions of edges, which significantly exceeds the device memory capacity of Graphics Processing Units (GPUs). The triangle counting problem is a broad research topic in data mining and social network analysis in the graph processing field. As the scale of the graph data grows, a portion of the graph data must be loaded iteratively. In the existing literature, graphs with billions of edges need to be done distributively, which is cost-intensive. Also, many disk-based triangle counting systems are proposed for CPU architectures, but their tackling performances are inefficient. To solve the above problem, we propose $TC$ T C - $Stream$ S t r e a m , and it focuses on three issues: 1) For power-law graphs, because the amount of tasks of each vertex or edge is inconsistent, it is bound to cause different demands of computing and memory resources for different task types. We propose a parallel vertex approach and the reordering of vertices for graph data that can be placed in the GPU device memory to ensure the maximum workload balancing; 2) A binary-search-based set intersection method is designed to achieve the maximum parallelism in GPU; 3) For the graph data that exceeds the GPU device memory capacity, we develop a novel vertical partition algorithm to guarantee the independent computing on each partition so that the three computation processes, i.e., the computation on GPU, the data transmission between main memory of CPU and SSD, and the communication between the CPU and the GPU can be perfectly overlapped. Moreover, the $TC$ T C - $Stream$ S t r e a m optimizes edge-iterator models and benefits from multi-thread parallelism. Extensive experiments conducted on large-scale datasets showed that the $TC$ T C - $stream$ s t r e a m running on a single Tesla V100 GPU performs $2.4-6\times$ 2. 4 - 6 × and $1.8-4.4\times$ 1. 8 - 4. 4 × faster than the state-of-the-art single-machine in-memory triangle counting system and GPU-based triangle counting system, respectively, and achieves $2.4\times$ 2. 4 × faster than the state-of-the-art out-of-core distributed system PDTL running on an 8-node cluster when processing the graph data with 42.5 billion edges, which demonstrates the high performance and cost-effectiveness of the $TC$ T C - $Stream$ S t r e a m . [ABSTRACT FROM AUTHOR]

Current edge computing systems are deployed in highly complex application scenarios with dynamically changing requirements. In order to provide the expected performance and energy efficiency values in these situations, the use of heterogeneous hardware/software platforms at the edge has become widespread. However, these computing platforms still suffer from the lack of unified software-driven programming models to efficiently deploy multi-purpose hardware-accelerated solutions. In parallel, edge computing systems also face another huge challenge: operating under multiple conditions that were not taken into account during any of the design stages. Moreover, these conditions may change over time, forcing self-adaptation mechanisms to become a must. This paper presents an integrated architecture to exploit hardware-accelerated data-parallel models and transparent hardware/software multithreading. In particular, the proposed architecture leverages the ARTICo3 framework and ReconOS to allow developers to select the most suitable programming model to deploy their edge computing applications onto run-time reconfigurable hardware devices. An evolvable hardware system is used as an additional architectural component during validation, providing support for continuous lifelong learning in smart edge computing scenarios. In particular, the proposed setup exhibits online learning capabilities that include learning by imitation from software-based reference algorithms. Experimental results show the benefits of the proposed approach, exposing different run-time tradeoffs (e.g., computing performance versus functional correctness of the evolved solutions), and highlighting the benefits of using scalable data-parallel models to perform circuit evolution under dynamically changing application scenarios. [ABSTRACT FROM AUTHOR]

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage. In this paper we introduce a precision-scalable integrated Photonic-Electronic Multiply-Accumulate Neuron (PEMAN). The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). Simulations are based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front-end. The PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed and power consumption with resolution, significantly outperforming its analog electronics counterparts both in terms of speed and energy consumption. With respect to other photonic ANNs, the PEMAN has comparable speed and energy consumption with a higher resolution, while outperforming them by a hundredfold in the fan-in, which opens the possibility to accelerate more complex networks. [ABSTRACT FROM AUTHOR]

In-package DRAM cache provides a higher bandwidth than conventional memory systems. Adapting the cache management to the run-time characteristics of each application seems a promising approach improving bandwidth efficiency and performance. Regrettably, fine-grained cache block monitoring and adaptation often becomes impractical due to its significant bandwidth, performance and hardware overheads. This paper proposes a novel mechanism for monitoring cache blocks using two parameters that are adjustable at run time. We propose two low-cost counter-based mechanisms to realize the block monitors in DRAM. Moreover, we propose a novel scheduling mechanism that opportunistically transfers the counter information to the DRAM stack when the data movement overhead reaches its minimum. Our simulation results on a set of data intensive parallel applications indicate that the proposed mechanisms achieve averages of 31%, 24% performance improvements over the state-of-the-art DRAM cache architectures. System energy savings over the same baselines are 29%, 18% on average. [ABSTRACT FROM AUTHOR]

Image captioning is a challenging task, i.e., given an image machine automatically generates natural language that matches its semantic content and has attracted much attention in recent years. However, most existing models are designed manually, and their performance depends heavily on the expert experience of the designer. In addition, the computational flow of the model is predefined, and hard and easy samples will share the same coding path and easily interfere with each other, thus confusing the learning of the model. In this paper, we propose a Dynamic Transformer to change the encoding procedure from sequential to adaptive, i.e., data-dependent computing paths. Specifically, we design three different types of visual feature extraction blocks and deploy them in parallel at each layer to construct a multi-layer routing space in a fully connected manner. Each block contains a calculation unit that performs the corresponding operations and a routing gate that learns to adaptively select the direction to pass the signal based on the input image. Thus, our model can achieve a robust visual representation by exploring potential visual feature extraction paths. We evaluate our method quantitatively and qualitatively using a benchmark MSCOCO image caption dataset and perform extensive ablation studies to investigate the reasons behind its effectiveness. The experimental results show that our method is significantly superior to previous state-of-the-art methods. [ABSTRACT FROM AUTHOR]

A common problem of the virtualized cloud radio access network architecture (C-RAN) is the compression of the time-domain IQ samples before transmission over the fronthaul link. Considering a multicarrier waveform such as OFDM, whose IQ samples follow a quasi-Gaussian distribution, the conventional Gaussian quantizer may be used as the optimal solution to the compression problem. However, since the high peak-to-average power ratio (PAPR) of OFDM signals remains a serious problem, various techniques may be employed to reduce the time-domain fluctuations of the IQ samples in the OFDM, resulting in a change in its distribution. The latter fact makes the Gaussian quantizer suboptimal. The literature lacks a performance analysis of the conventional OFDM-based compression techniques when the PAPR of the OFDM signal is reduced. Therefore, in this paper, we study for the first time the impact of reducing the PAPR of the OFDM signal before compression in the C-RAN architecture through rate-distortion analysis. We consider clipping and tone reservation PAPR reduction algorithms. The former is the simplest PAPR reduction approach, while the latter is one of the most effective algorithms used in broadcasting standards such as DVB-T2 and ATSC 3.0. We first derive the distribution of the PAPR-reduced OFDM IQ samples. This is used to optimize the thresholds and codebook levels of a non-uniform scalar quantizer and the number of quantization bits allocated for each quantized level in the entropy coding stage, along with the MER performance analysis. The simulation results show that the conventional Gaussian-based compression techniques applied to a PAPR-reduced signal is not very robust to the statistical changes in the signal unless the signal distribution at the input of the Gaussian quantizer is not significantly affected. However, a significant gain is obtained when the quantizer is optimized with respect to the true distribution of the PAPR-reduced IQ samples. [ABSTRACT FROM AUTHOR]

Existing RGB-D salient object detection (SOD) models usually treat RGB and depth as independent information and design separate networks for feature extraction from each. Such schemes can easily be constrained by a limited amount of training data or over-reliance on an elaborately designed training process. Inspired by the observation that RGB and depth modalities actually present certain commonality in distinguishing salient objects, a novel joint learning and densely cooperative fusion (JL-DCF) architecture is designed to learn from both RGB and depth inputs through a shared network backbone, known as the Siamese architecture. In this paper, we propose two effective components: joint learning (JL), and densely cooperative fusion (DCF). The JL module provides robust saliency feature learning by exploiting cross-modal commonality via a Siamese network, while the DCF module is introduced for complementary feature discovery. Comprehensive experiments using five popular metrics show that the designed framework yields a robust RGB-D saliency detector with good generalization. As a result, JL-DCF significantly advances the state-of-the-art models by an average of $\sim 2.0\%$ ∼ 2. 0 % (max F-measure) across seven challenging datasets. In addition, we show that JL-DCF is readily applicable to other related multi-modal detection tasks, including RGB-T (thermal infrared) SOD and video SOD, achieving comparable or even better performance against state-of-the-art methods. We also link JL-DCF to the RGB-D semantic segmentation field, showing its capability of outperforming several semantic segmentation models on the task of RGB-D SOD. These facts further confirm that the proposed framework could offer a potential solution for various applications and provide more insight into the cross-modal complementarity task. [ABSTRACT FROM AUTHOR]

Few-shot learning under the $N$ N -way $K$ K -shot setting (i.e., $K$ K annotated samples for each of $N$ N classes) has been widely studied in relation extraction (e.g., FewRel) and image classification (e.g., Mini-ImageNet). Named entity recognition (NER) is typically framed as a sequence labeling problem where the entity classes are inherently entangled together because the entity number and classes in a sentence are not known in advance, leaving the $N$ N -way $K$ K -shot NER problem so far unexplored. In this paper, we first formally define a more suitable $N$ N -way $K$ K -shot setting for NER. Then we propose FewNER, a novel meta-learning approach for few-shot NER. FewNER separates the entire network into a task-independent part and a task-specific part. During training in FewNER, the task-independent part is meta-learned across multiple tasks and the task-specific part is learned for each individual task in a low-dimensional space. At test time, FewNER keeps the task-independent part fixed and adapts to a new task via gradient descent by updating only the task-specific part, resulting in it being less prone to overfitting and more computationally efficient. Compared with pre-trained language models (e.g., BERT and ELMo) which obtain the transferability in an implicit manner (i.e., relying on large-scale corpora), FewNER explicitly optimizes the capability of “learning to adapt quickly” through meta-learning. The results demonstrate that FewNER achieves state-of-the-art performance against nine baseline methods by significant margins on three adaptation experiments (i.e., intra-domain cross-type, cross-domain intra-type and cross-domain cross-type). [ABSTRACT FROM AUTHOR]

Mobile terminals have been widely used in the communication applications (e.g., vehicular network, e-Health, smart grid and e-Commerce) as they can obtain all kinds of services and upload data for users anytime and anywhere. With the number of users increasing dramatically and user demands diversifying, multi-server architecture was proposed to solve issues on lack of service resources that single-server architecture remains. However, multi-server architecture faces a series of challenges in applications, such as security and authentication efficiency requirements. Thus, many authenticated key agreement (AKA) protocols are presented, yet most of them require unacceptable computation and communication overhead, which is inefficient indeed. In this paper, we propose an adaptive secure handover authenticated key agreement protocol for multi-server architecture. Specifically, broadcast mechanism is utilized to assist users to select appropriate service providers with the lowest cost. Users can realize efficient handover authentication with multiple servers in the proposed scheme, that is, after completing initial authentication, users can switch to other servers and complete authentication through simple operations. Security analysis shows the proposed protocol can meet all security requirements and compared with other relevant protocols, it greatly reduces the computation and communication overhead. In addition, the above advantages grow significantly as the number of servers to be authenticated increases. [ABSTRACT FROM AUTHOR]

The acceleration of CNNs has gained increasing attention since their success in computer vision. Since the heterogeneous layers cannot be processed by accelerators proposed for convolution layers only, modern end-to-end CNN acceleration solutions either transform diverse computation into matrix/vector arithmetic, which loses data reuse opportunities in convolution, or introduce dedicated functional unit to each kind of layer, which results in underutilization and high update expenses. To enhance the whole-life cost efficiency, we need a solution that is efficient in processing CNN layers and has the generality to apply to all kinds of existing and emerging layers. To this end, we propose GCONV Chain, a method to convert the entire CNN computation into a chain of standard general convolutions (GCONV) that can be efficiently processed by existing CNN accelerators with low-overhead hardware support. This paper comprehensively analyzes the GCONV Chain model and proposes a full-stack implementation to support GCONV Chain. Our results on various CNNs demonstrate that GCONV Chain improves the performance and energy efficiency of existing CNN accelerators by an average of 3.4x and 3.2x respectively. Furthermore, we show that GCONV Chain provides low whole-life costs for CNN acceleration, including both developer efforts and total cost of ownership. [ABSTRACT FROM AUTHOR]

Processing-in-memory (PIM) architectures have demonstrated great potential in accelerating numerous deep learning tasks. Particularly, resistive random-access memory (RRAM) devices provide a promising hardware substrate to build PIM accelerators due to their abilities to realize efficient in-situ vector-matrix multiplications (VMMs). However, existing PIM accelerators suffer from frequent and energy-intensive analog-to-digital (A/D) conversions, severely limiting their performance. This paper presents a new PIM architecture to efficiently accelerate deep learning tasks by minimizing the required A/D conversions with analog accumulation and neural approximated peripheral circuits. We first characterize the different dataflows employed by existing PIM accelerators, based on which a new dataflow is proposed to remarkably reduce the required A/D conversions for VMMs by extending shift and add (S+A) operations into the analog domain before the final quantizations. We then leverage a neural approximation method to design both analog accumulation circuits (S+A) and quantization circuits (ADCs) with RRAM crossbar arrays in a highly-efficient manner. Finally, we apply them to build a RRAM-based PIM accelerator (i.e., Neural-PIM) upon the proposed analog dataflow and evaluate its system-level performance. Evaluations on different benchmarks demonstrate that Neural-PIM can improve energy efficiency by $5.36\times$ 5. 36 × ($1.73\times$ 1. 73 × ) and speed up throughput by $3.43\times$ 3. 43 × ($1.59\times$ 1. 59 × ) without losing accuracy, compared to the state-of-the-art RRAM-based PIM accelerators, i.e., ISAAC [1] (CASCADE [2]). [ABSTRACT FROM AUTHOR]

Emerging device based spiking neural network (SNN) hardware design has been actively studied. Especially, energy and area efficient synapse crossbar has been of particular interest, but processing units for weight summations in synapse crossbar are still a main bottleneck for energy and area efficient hardware design. In this paper, we propose an efficient SNN architecture with stochastic spin-orbit torque (SOT) device based multi-bit synapses. First, we present SOT device based synapse array using modified gray code. The modified gray code based synapse needs only N devices to represent 2N levels of synapse weights. Accumulative spike technique is also adopted in the proposed synapse array, to improve ADC utilization and reduce the number of neuron updates. In addition, we propose hardware friendly algorithmic techniques to improve classification accuracies as well as energy efficiencies. Non-spike depression based stochastic spike-timing-dependent plasticity is used to reduce the overlapping input representation and classification error. Early read termination is also employed to reduce energy consumption by turning off less associated neurons. The proposed SNN processor has been implemented using 65nm CMOS process, and it shows 90% classification accuracy in MNIST dataset consuming 0.78μJ/image (training) and 0.23μJ/image (inference) of energy with an area of 1.12mm2. [ABSTRACT FROM AUTHOR]

The papers in this special section focus on software, hardware, and computer applications for neuromorphic computing. Inspired by biological neural systems, neuromorphic computing has drawn much attention for its great potential of achieving machine intelligence at extremely low energy dissipation. Bio-inspired computing models have been investigated for information encoding, sparse representation, event driven communication/computation, and online learning. This new computing paradigm triggered a recent wave of innovations in software and hardware architecture and emerging device technology, which consequently enabled many novel applications. This is an exemplar of research area where the application, computing model, architecture and circuit level design are tightly coupled to deliver unprecedented functionality and energy efficiency. [ABSTRACT FROM AUTHOR]

Road detection is a critically important task for self-driving cars. By employing LiDAR data, recent works have significantly improved the accuracy of road detection. However, relying on LiDAR sensors limits the application of those methods when only cameras are available. In this paper, we propose a novel road detection approach with RGB images being the only input. Specifically, we exploit pseudo-LiDAR using depth estimation and propose a feature fusion network in which RGB images and learned depth information are fused for improved road detection. To optimize the network architecture and improve the efficiency of our network, we propose a method to search for the information propagation paths. Finally, to reduce the computational cost, we design a modality distillation strategy to avoid using depth estimation networks during inference. The resulting model eliminates the reliance on LiDAR sensors and achieves state-of-the-art performance on two challenging benchmarks, KITTI and R2D. [ABSTRACT FROM AUTHOR]

Recognition and localization models can be generally decomposed into three components: encoder, decoder, and task head. In this paper, we rethink the necessity of decoder, as we observe that it brings additional computational and parametric burden. We thus propose to remove the decoder and present a bidirectional cross-scale architecture that is able to obtain rich semantic information and precise localization in a unified backbone. Extensive experiments demonstrate that, different from common encoder-decoder models and other down-sampling and up-sampling backbones, the proposed BiCSNet achieves improved performances compared to existing architectures for pixel-level tasks. In object detection, our BiCSNet brings significant performance improvement by ~ 3% AP at various scales with 13% – 23% fewer FLOPS, compared with ResNet-FPN models on COCO dataset. In Instance segmentation, the AP can be improved by 1% over SpineNet. BiCSNet is also promising for semantic segmentation tasks, as the proposed BiCSNet pre-trained on ImageNet alone significantly outperforms DeepLabv3 pre-trained on both ImageNet and COCO dataset by 1.3% in mIOU with 89% fewer FLOPs on PASCAL VOC 2012. [ABSTRACT FROM AUTHOR]