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In this paper, a simple yet effective network pruning framework is proposed to simultaneously address the problems of pruning indicator, pruning ratio, and efficiency constraint. This paper argues that the pruning decision should depend on the convolutional weights, and thus proposes novel weight-dependent gates (W-Gates) to learn the information from filter weights and obtain binary gates to prune or keep the filters automatically. To prune the network under efficiency constraints, a switchable Efficiency Module is constructed to predict the hardware latency or FLOPs of candidate pruned networks. Combined with the proposed Efficiency Module, W-Gates can perform filter pruning in an efficiency-aware manner and achieve a compact network with a better accuracy-efficiency trade-off. We have demonstrated the effectiveness of the proposed method on ResNet34, ResNet50, and MobileNet V2, respectively achieving up to 1.33/1.28/1.1 higher Top-1 accuracy with lower hardware latency on ImageNet. Compared with state-of-the-art methods, W-Gates also achieves superior performance. [ABSTRACT FROM AUTHOR]

E-beam voltage contrast inspection is a very common method for in-line detection of many key defect types for rapid yield learning during technology development. Generally, the wafer surface is charged positive, but sometimes charging the wafer surface negative makes more sense. This paper reviews four advantages that negative charging may provide. Switching from positive to negative charging is typically achieved using landing energy and/or extraction voltage. A third control knob is introduced and demonstrated using three common inspection layers, contact chemical mechanical polish (CMP), 3D NAND wordline shorts and 3D NAND wordline opens. [ABSTRACT FROM AUTHOR]

This paper studies the precoder design problem of achieving max-min fairness (MMF) amongst users in multigateway multibeam satellite communication systems with feeder link interference. We propose a beamforming strategy based on a newly introduced transmission scheme known as rate-splitting multiple access (RSMA). RSMA relies on multi-antenna rate-splitting at the transmitter and successive interference cancellation (SIC) at the receivers, such that the intended message for a user is split into a common part and a private part and the interference is partially decoded and partially treated as noise. In this paper, we formulate the MMF problem subject to per-antenna power constraints at the satellite for the system with imperfect channel state information at the transmitter (CSIT). We also consider the case of two-stage precoding which is assisted by on- board processing (OBP) at the satellite. Numerical results obtained through simulations for RSMA and the conventional linear precoding method are compared. When RSMA is used, MMF rate gain is promised and this gain increases when OBP is used. RSMA is proven to be promising for multigateway multibeam satellite systems whereby there are various practical challenges such as feeder link interference, CSIT uncertainty, per-antenna power constraints, uneven user distribution per beam and frame-based processing. [ABSTRACT FROM AUTHOR]

XOR-AND Graphs (XAGs) are an enrichment of the classical AND-Inverter Graphs (AIGs) with XOR nodes. In particular, XAGs are networks composed by ANDs, XORs, and inverters. Besides several emerging technologies applications, XAGs are often exploited in cryptography-related applications based on the multiplicative complexity of a Boolean function. The multiplicative complexity of a function is the minimum number of AND gates (i.e., multiplications) that are sufficient to represent the function over the basis {AND, XOR, NOT}. In fact, the minimization of the number of AND gates is important for high-level cryptography protocols such as secure multiparty computation, where processing AND gates is more expensive than processing XOR gates. Moreover, it is an indicator of the degree of vulnerability of the circuit, as a small number of AND gates corresponds to a high vulnerability to algebraic attacks. In this paper we study the multiplicative complexity of Boolean functions characterized by two particular regularities, called autosymmetry and D-reducibility. Moreover, we exploit these regularities for decreasing the number of AND nodes in XAGs. The experimental results validate the proposed approaches. [ABSTRACT FROM AUTHOR]

The cross-domain image captioning, which is trained on a source domain and generalized to other domains, usually faces the large domain shift problem. Although prior work has attempted to leverage both paired source and unpaired target data to minimize this shift, the performance is still unsatisfactory. One main reason lies in the large discrepancy in language expression between two domains, where diverse language styles are adopted to describe an image from different views, resulting in different semantic descriptions for an image. To tackle this problem, this paper proposes a Style-based Cross-domain Image Captioner (SCIC) which incorporates the discriminative style information into the encoder-decoder framework, and interprets an image as a special sentence according to external style instructions. Technically, we design a novel “Instruction-based LSTM”, which adds the instruct gate to collect a style instruction, and then outputs a specified format according to that instruction. Two objectives are designed to train I-LSTM: 1) generating correct image descriptions and 2) generating correct styles, thus the model is expected to accurately capture the semantic meanings of an image by the special caption as well as understand the syntactic structure of the caption. We use MS-COCO as the source domain, and Oxford-102, CUB-200, Flickr30k as the target domains. Experimental results demonstrate that our model consistently outperforms the previous methods, and the style information incorporating with I-LSTM significantly improves the performance, with 5% CIDEr improvements at least on all datasets. [ABSTRACT FROM AUTHOR]

Contemporary and emergent automotive systems are heavily populated by complex integrated electronics. The number of safety-critical devices used in advanced driver-assistance systems or autonomous vehicles is growing with high-end models containing hundreds of embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that might be costly to engineer. Therefore, to address challenges posed by high-quality and long-term reliability requirements, this article presents low-cost test pattern generation schemes for a scan-based hybrid logic BIST of automotive ICs. It may allow one to optimize test coverage and test time during in-system test applications. The first presented technique deploys a seed-flipping PRPG to periodically complement PRPG stages in a methodical tree-traversal manner. The second scheme is based on a seed-sorting approach that allows additional tradeoffs between test data volume and test coverage. As shown in this article, the proposed schemes can be easily integrated with a test compression environment and deployed in different modes of in-system testing, such as key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes. [ABSTRACT FROM AUTHOR]

This article addresses polynomial computation with unipolar stochastic logic by exploiting correlation between the bit-streams. The AND-OR, double-NAND, OR-AND and double-NOR circuits are presented for polynomials with all positive coefficients whose sum is less than or equal to one by mathematically analyzing the joint probability distribution of coefficient bit-streams. The NAND-AND expansion is also developed for polynomials with alternatively positive and negative coefficients whose absolute values are decreasing by applying the same idea. Unlike the original methods with multiple uncorrelated random number sources (RNSs) for coefficient bit-stream generation, the presented methods only require a single RNS. Since the RNSs take up huge hardware resource in stochastic circuits, the proposed RNS-sharing techniques for polynomial computation result in a significant reduction of hardware complexity. For the factorization technique in the general polynomials, this paper enhances the original stochastic designs for the second-order polynomial and further presents the simple correlation-dependent circuits. Results show that the proposed architectures are superior to the previous ones by reducing the total number of RNSs. [ABSTRACT FROM AUTHOR]

In conventional star-topology LoRa networks, the gateways are expected to collect the data from all the nodes nearby. However, a major challenge for the conventional LoRa system is the performance degradation due to the long-range communication over fading channels. To resolve the challenging issue, this paper investigates a two-hop amplify-and-forward relaying LoRa network in a two-dimension plane, where random nodal distances are considered. Moreover, a relay-selection mechanism is developed for the proposed system. Based on the best relay-selection protocol, the analytical bit-error-rate (BER) and asymptotic BER expressions, achievable diversity order, coverage probability, and throughput of the proposed system are derived over the Nakagami- $m$ fading channel. Furthermore, to maximize the throughput of the proposed system, a two-dimensional resource allocation optimization problem (i.e., the spread factor selection and power allocation optimization) is formulated and investigated. The proposed optimal spread factor selection and power allocation scheme is verified to outperform the two baseline schemes. Simulation and numerical results show that although the proposed system reduces the throughput compared to the conventional LoRa system, it significantly improves the BER and coverage probability. Hence, the proposed system can be considered as a promising technique for low-power, long-range and highly reliable Internet-of-Things applications. [ABSTRACT FROM AUTHOR]

Grounding referring expressions in images aims to locate the object instance in an image described by a referring expression. It involves a joint understanding of natural language and image content, and is essential for a range of visual tasks related to human-computer interaction. As a language-to-vision matching task, the core of this problem is to not only extract all the necessary information (i.e., objects and the relationships among them) in both the image and referring expression, but also make full use of context information to align cross-modal semantic concepts in the extracted information. Unfortunately, existing work on grounding referring expressions fails to accurately extract multi-order relationships from the referring expression and associate them with the objects and their related contexts in the image. In this paper, we propose a cross-modal relationship extractor (CMRE) to adaptively highlight objects and relationships (spatial and semantic relations) related to the given expression with a cross-modal attention mechanism, and represent the extracted information as a language-guided visual relation graph. In addition, we propose a Gated Graph Convolutional Network (GGCN) to compute multimodal semantic contexts by fusing information from different modes and propagating multimodal information in the structured relation graph. Experimental results on three common benchmark datasets show that our Cross-Modal Relationship Inference Network, which consists of CMRE and GGCN, significantly surpasses all existing state-of-the-art methods. [ABSTRACT FROM AUTHOR]

In recent years, very high frequency (VHF) converter has attracted much attention. However, with rich parasitic parameters and complex resonance links, there are some great difficulties to the modeling of such systems. Taking the on-off controlled VHF resonant boost converter as an example, this paper presents an accurate modeling and analysis method that considers multiple parasitic parameters. First, the closed-loop VHF converter system is divided into a main network and a parasitic oscillation network. Then, based on the operation analysis, an equivalent circuit model characterized by a time-varying input voltage source and two variable duty-cycle controlled switches is proposed. It worth noting that both the time-varying input and the controlled switches take into account the influences of the parameters. Furthermore, the periodic approximate analytical solution of the output voltage in the on stage is obtained by using the equivalent small parameter method to the proposed circuit model. And then combining the solution of the parasitic oscillation network and on-off state switching conditions, the steady-state waveform of output voltage can be obtained quickly. Finally, a prototype with operating frequency of 21.44 MHz is built to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Existing crowd counting approaches predominantly perform well on the training-testing protocol. However, due to large style discrepancies not only among images but also within a single image, they suffer from obvious performance degradation when applied to unseen domains. In this paper, we aim to design a generalizable crowd counting framework which is trained on a source domain but can generalize well on the other domains. To reach this, we propose a gated ensemble learning framework. Specifically, we first propose a diverse fine-grained style attention model to help learn discriminative content feature representations, allowing for exploiting diverse features to improve generalization. We then introduce a channel-level binary gating ensemble model, where diverse feature prior, input-dependent guidance and density grade classification constraint are implemented, to optimally select diverse content features to participate in the ensemble, taking advantage of their complementary while avoiding redundancy. Extensive experiments show that our gating ensemble approach achieves superior generalization performance among four public datasets. Codes are publicly available at https://github.com/wdzhao123/DCSL. [ABSTRACT FROM AUTHOR]

Due to the deployment of 5G technology, the number of IoV (Internet of Vehicle) devices connected to the Internet will explosively grow. However, as a kind of edge network device, IoV devices also face some problems including weak password authentication, lack of security protection, and lagged firmware updating, which largely threaten the security and legitimacy of these devices. IoV device identification is important in discovering, monitoring, and protecting these devices. Although existing proactive identification methods based on device fingerprints can be used to identify the large-scale Internet-connected IoV devices, they can not meet the fine-grained requirements for security risk assessment. Due to the increase in the types and brands of IoV devices, the fingerprint granularity will be insufficient. In this paper, we proposed a retransmission-based TCP fingerprints for large-scale fine-grained proactive device identification. Firstly, a probing scheme was designed to obtain TCP retransmission packet and increase the granularity space of traditional TCP fingerprint by selecting the multi-group features of TCP retransmission messages. Then, according to the bagging strategy of ensemble learning, a combined classifier with five predominant machine learning algorithms was generated. The experimental results showed that the identification accuracy and recall of IoV devices respectively reached 96.7% and 95.2%. [ABSTRACT FROM AUTHOR]

In general, a power transformer is equipped with differential protection relay with the second harmonic restraint criterion to improve reliability. However, this criterion may fail in some cases, resulting in incorrect operation of protection relay. Therefore, to further upgrade the performance of differential protection, this paper proposes a duty cycle-based scheme as complement. Firstly, the waveform of the differential current in one cycle and its two derived waveforms, constructed by translating and taking absolute, are transformed into corresponding square waves, respectively. Then, duty cycles of these square waves are calculated, and three criteria are presented to quantify the differences between the duty cycles of disturbances and faults. Finally, the criteria and the second harmonic restraint are combined through three logic gates to form the proposed scheme for protection. A large number of simulation experiments have verified the effectiveness of the proposed scheme, which outperforms the frequently used protection schemes. [ABSTRACT FROM AUTHOR]

In this paper, we study the problem of learning an unknown quantum circuit of a certain structure. If the unknown target is an $n$ -qubit Clifford circuit, we devise an efficient algorithm to reconstruct its circuit representation by using $O(n^{2})$ queries to it. For decades, it has been unknown how to handle circuits beyond the Clifford group since the stabilizer formalism cannot be applied in this case. Herein, we study quantum circuits of $T$ -depth one on the computational basis. We show that the output state of a $T$ -depth one circuit can be represented by a stabilizer pseudomixture with a specific algebraic structure. Using Pauli and Bell measurements on copies of the output states, we can generate a hypothesis circuit that is equivalent to the unknown target circuit on computational basis states as input. If the number of $T$ gates of the target is of the order $O({\log n})$ , our algorithm requires $O(n^{2})$ queries to it and produces its equivalent circuit representation on the computational basis in time $O(n^{3})$. Using further additional $O(4^{3n})$ classical computations, we can derive an exact description of the target for arbitrary input states. Our results greatly extend the previously known facts that stabilizer states can be efficiently identified based on the stabilizer formalism. [ABSTRACT FROM AUTHOR]

Many studies focusing on integrating reviews with ratings to improve recommendation performance have been quite successful. However, these works still face several shortcomings: (1) The importance of dynamically integrating review and interaction data features is typically ignored, yet treating these fusion features equally may lead to an incomplete understanding of user preferences. (2) Some forms of soft attention methods are adopted to model the local semantic information of words. As features thus captured may contain irrelevant information, the generated attention map is neither discriminatory nor detailed. In this paper, we propose a novel Adaptive Hierarchical Attention-enhanced Gated network integrating reviews for item recommendation, named AHAG. AHAG is a unified framework to capture the hidden intentions of users by adaptively incorporating reviews. Specifically, we design a gated network to dynamically fuse the extracted features and select the features that are most relevant to user preferences. To capture distinguishing fine-grained features, we introduce a hierarchical attention mechanism to learn important semantic information features and the dynamic interaction of these features. Besides, the high-order non-linear interaction of neural factorization machines is utilized to derive the rating prediction. Experiments on seven real-world datasets show that the proposed AHAG significantly outperforms state-of-the-art methods. Furthermore, the attention mechanism can highlight the relevant information in reviews to increase the interpretability of the recommendation task. Source codes are available in https://github.com/luojia527/AHAG. [ABSTRACT FROM AUTHOR]

Personalized location prediction is key to many mobile applications and services. In this paper, motivated by both statistical and visualized preliminary analysis on three real datasets, we observe a strong spatiotemporal correlation for user trajectories among the visited area-of-interests (AoIs) and different time periods on both weekly and daily basis, which directly motivates our time-aware location prediction model design called “ $t$ t -LocPred”. It models the spatial correlations among AoIs by coarse-grained convolutional processing of the user trajectories in AoIs of different time periods (“ConvAoI”); and predicts his/her fine-grained next visited PoI using a novel memory-augmented attentive LSTM model (“mem-attLSTM”) to capture long-term behavior patterns. Experimental results show that $t$ t -LocPred outperforms 8 baselines. We also show the impact of hyperparameters and the benefits ConvAoI can bring to these baselines. [ABSTRACT FROM AUTHOR]

The Hidden Weighted Bit function plays an important role in the study of classical models of computation. A common belief is that this function is exponentially hard to implement using reversible ancilla-free circuits, even though introducing a small number of ancillae allows a very efficient implementation. In this paper, we refute the exponential hardness conjecture by developing a polynomial-size reversible ancilla-free circuit computing the Hidden Weighted Bit function. Our circuit has size $O(n^{6.42})$ O (n 6. 42) , where $n$ n is the number of input bits. We also show that the Hidden Weighted Bit function can be computed by a quantum ancilla-free circuit of size $O(n^2)$ O (n 2) . The technical tools employed come from a combination of Theoretical Computer Science (Barrington's theorem) and Physics (simulation of fermionic Hamiltonians) techniques. [ABSTRACT FROM AUTHOR]

Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation, and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a hardware description language (HDL)-based modeling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit’s invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit cyclic redundancy check (CRC) circuit. The system modeled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems. [ABSTRACT FROM AUTHOR]

With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This article first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this article also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2, 32.8, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called high-impedance state-insensitive, TNU-tolerant, and SET-filterable latch can reduce delay, power, and area by 78.9, 15.8, and 28.6%, respectively, compared with the state-of-the-art TNU hardened latch. [ABSTRACT FROM AUTHOR]

In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.

Undetectable faults result from logic redundancies and constraints on applicable tests. The presence of an undetected (undetectable or aborted) fault implies that a test, which would have covered its site, is missing from the test set. When undetected transition faults form a path, the missing tests imply that (small) delay defects along the path may not be detected even if they are detectable. The goal of this article is to provide additional coverage for paths of undetected transition faults by using two-cycle gate-exhaustive faults for subcircuits (gates) that wrap the paths. The use of gate-exhaustive faults alleviates the need to model delay defects along the paths, or use path delay faults that may also be undetectable. The article defines the target paths, and gates that wrap them, for which two-cycle gate-exhaustive faults can be defined. Experimental results for benchmark circuits demonstrate the discussion. [ABSTRACT FROM AUTHOR]

With the emergence of the multicore architecture and the increase of chip operating frequency, power optimization has become a key step of circuit logic synthesis. Aiming at the XNOR/OR circuits, with the goal of minimizing power, construct the optimal polarity fixed-polarity Reed–Muller (FPRM) circuits power optimization scheme. However, the power optimization for FPRM circuits is a multipeak combinatorial optimization problem, we first propose a metaheuristic optimization algorithm (MOA), which includes the global exploration optimizer, local deep exploitation optimizer, and initial population and uses the proposed differential evolution optimization, fierce wolf siege algorithm-based tabu search, and improved skew tent map to make the population evolve. Based on the proposed Huffman tree construction algorithm and MOA, we propose an efficient power optimization approach (EPOA) to find the minimum power FPRM circuit. Experimental results on the benchmark circuits confirm the effectiveness of EPOA. [ABSTRACT FROM AUTHOR]

The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads. Finding a feasible worst case workload is difficult due to logical correlation within the logic circuit under consideration. In this article, we propose an NBTI-aware subset simulation (SS) framework that efficiently and accurately finds the failure probability covering various input duty cycles determined by different workloads. In addition, the proposed method is incorporated with the NBTI mitigation technique to facilitate workload-aware mitigation. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to a naive Monte Carlo method. The NBTI mitigation based on SS demonstrates $1.78\times $ better mitigation for multiple input duty cycles compared to the conventional method. [ABSTRACT FROM AUTHOR]

Transforming into an agile organization is challenging because it involves complex changes across the organization including changes to strategy, structure, culture, operations, and technology. Although much has been written about organizational agility, practitioners still call for authentic accounts and concrete experiences to help them understand how to transform. This article is based on three case studies of diverse organizations transforming to agility and provides an account of each transformation. Each organization chose a different focus for their transformation: culture change, strategic change, and operational change. Each organization faced challenges that resulted in tensions. We present 13 tensions from three cases, which illustrate the kinds of tension that organizations face in agile transformations. We consider these 13 tensions through the lens of paradox theory and thereby produce both practical guidance and theoretical contributions. We show how questions generated from this perspective may be used to guide transformation leaders and managers in addressing the tensions they will meet. Our findings provide empirical evidence for the tension categories in paradox theory and show that tensions occur during transformations to agility and not just in fully agile organizations. [ABSTRACT FROM AUTHOR]

The single gate driven series connected power device stack possesses the advantages of high compactness and low cost. However, research of its short circuit (SC) characteristic remains uncovered. This article fills this gap and points out that, with the single gate driver it has the potential of over-current limitation. Furthermore, based on it, an improved single gate driven silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfet) stack with strong antishort circuit fault capabilities is proposed. By adding auxiliary circuits to adjust the driving process of the single gate driver, the SiC mosfet stack can be automatically turned off in both SC conditions of fault under load and hard switch fault, while the normal working principle of the stack is not influenced. Neither active control nor overcurrent detection is required, which is the biggest merit of the proposed topology. Its design and analysis are presented in detail, followed by the validation by conducting simulations and experiments. [ABSTRACT FROM AUTHOR]

Advanced field-effect transistors (FETs), such as gate-all-around (GAA) nanowire (NW) and nanosheet (NS) devices, have been highly scaled; therefore, they are critically affected even by a microscopic fluctuation. As the GAA NS device is considered a promising candidate beyond 5-nm technology, it is essential to analyze the effects of these fluctuations on dc and analog/radio frequency (RF) characteristics for future applications. In this article, we for the first time demonstrate that the machine learning (ML)-aided numerical device simulation approach can be used to model the effects of various fluctuations on the characteristics of GAA NS FETs (NSFETs). Among various fluctuations, we mainly focus on work function fluctuation (WKF), random dopant fluctuation (RDF), and interface trap fluctuation (ITF). The independent and combined effects of these fluctuations on the characteristics of NSFETs are studied. Except for transfer and output characteristics, analog and RF parameters, such as gate capacitance, transconductance, cutoff frequency, 3-dB frequency, and transconductance efficiency, are analyzed in detail. The main aim of this work is to show the capability and generality of ML in modeling various electrical characteristics of the explored NSFETs. The results show that the ML-based technique is fast and efficient, which accelerates the overall process and gives engineering acceptable accurate results. [ABSTRACT FROM AUTHOR]

This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows $>5\times $ reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself. [ABSTRACT FROM AUTHOR]

Logic obfuscation is introduced as a pivotal defense against multiple hardware threats on integrated circuits (ICs), including reverse engineering (RE) and intellectual property (IP) theft. The effectiveness of logic obfuscation is challenged by recently introduced Boolean satisfiability (SAT) attack and its variants. A plethora of counter measures have also been proposed to thwart the SAT attack. Irrespective of the implemented defense against SAT attacks, large power, performance, and area overheads are seen to be indispensable. In contrast, we propose a cognitive solution, which is a neural network (NN)-based SAT-hard clause translator, SATConda, that incurs a minimal area and power overhead while preserving the original functionality with enhanced security. SATConda is incubated with a SAT-hard clause generator that translates the existing conjunctive normal form (CNF) through minimal perturbations, such as the inclusion of pair of inverters or buffers or adding new lightweight SAT-hard block depending on the provided CNF. For efficient SAT-hard clause generation, SATConda is equipped with a multilayer NN that first learns the dependencies of features (literals and clauses), followed by a long short-term memory (LSTM) network to validate and backpropagate the SAT-hardness for better learning and translation. Our proposed SATConda is evaluated on ISCAS’85 and ISCAS’89 benchmarks and is seen to successfully defend against multiple state-of-the-art SAT attacks devised for hardware RE. In addition, we also evaluate our proposed SATConda’s empirical performance against MiniSAT, Lingeling, and Glucose SAT solvers that form the base for numerous existing deobfuscation SAT attacks. [ABSTRACT FROM AUTHOR]

Conventional digital LLC synchronous rectifier (SR) control typically uses detection circuits to sense the drain-source voltage of SR MOSFET in low output voltage applications, or gives SR duty cycle only considering the switching frequency in the microcontroller. They are difficult to be applied to the applications of 700-V high voltage and 6.6-kW high power directly due to the high dv/dt and large SR duty cycle variations, which poses serious challenge for SRs control. A bidirectional impedance-based SR driving scheme is presented for high-voltage SiC LLC converter. Based on the LLC equivalent impedance, mathematical models are built to calculate the SR on-time in the forward and reverse modes, which can be tuned timely when the switching frequency and load vary. Thus, both bidirectional LLC performance with high efficiency and high immunity to the switching noise can be achieved without adding auxiliary circuits. A prototype of 300-kHz 6.6-kW SiC bidirectional LLC charger was built. Compared to the conventional SR method, the LLC efficiencies improve 0.3% in the forward and reverse modes at full load by using the proposed SR driving scheme. [ABSTRACT FROM AUTHOR]

This brief presents an analog multiplier based controller for a noninverting buck-boost (NIBB) converter, in which the controller can work for both buck and boost modes of the NIBB converter, thus simplifying the design and saving the power and area for the controller. Moreover, it can obtain good line regulation and load regulation performances. The analog multiplier based controller can automatically change over between the buck and boost modes according to the input and output voltages. This brief, fabricated in 65-nm CMOS process, exhibits a core area of ${1}.{67}{\times }{0}.{64}{mm}^{2}$. It outputs a stable 0.9 V when the input voltage changes from 0.7-1.4 V, with a maximum output load current of 200 mA. [ABSTRACT FROM AUTHOR]

True random number generators (TRNGs) based on ring oscillators are employed in many devices because they can be constructed with logic gates only. Random numbers generated by TRNGs are used for various cryptographic systems as session keys, nonces, and masks. The randomness of a TRNG is characterized by uniformity, nonreproducibility, and unpredictability. Moreover, the quality of random numbers affects cryptographic systems. In particular, degradation of the unpredictability can reduce the security of the cryptographic system because random numbers can be easily estimated. Side-channel attacks, which exploit additional information leaked from a cryptographic module to reveal secret information, are well known. If some additional information reflecting the output bit can be measured from electromagnetic (EM) emission as a side-channel leakage against a TRNG, the unpredictability of the TRNG may decrease. Accordingly, this article introduces the leakage model that reflects an output bit generated by a transition effect ring oscillator (TERO) based TRNG, and an attack that estimates random number bits by measuring EM emission from an integrated circuit against TERO-based TRNG. We propose a leakage model against a TERO-based TRNG and demonstrate that the output bits of the TRNG can be estimated by analyzing the radiated emissions. We also consider a countermeasure against the proposed attack. [ABSTRACT FROM AUTHOR]

In the mm-wave frequency band, the rectifier’s sensitivity is the bottleneck of a wireless-powered IoT transponder’s distance. At a meter’s distance, the received power is weak, and transistors in a front end of a wireless power receiver operate in the weak inversion region. This article presents a mathematical analysis of the mm-wave multi-stage rectifier in the low-power region. A design methodology of a 57–64-GHz fully integrated eight-stage rectifier with a bulk-drain connection in 40-nm CMOS technology is presented. Parasitic effects on a multi-stage rectifier are analyzed. Based on the analysis, an intrinsic threshold voltage modulation is applied to improve the sensitivity. A tree-type power splitter is also proposed for the RF power signal’s phase balance. With this method, the RF signal arrives at each stage with an equal phase, and its suppression at the output is improved by 16 dB. This mm-wave rectifier achieves −7.1-dBm input sensitivity at 57 GHz with 1-V dc output voltage. The overall sensitivity from 57 to 64 GHz is better than −4.5 dBm. Compared to other mm-wave silicon-based rectifier state of the arts, the proposed mm-wave rectifier achieves better sensitivity while maintaining a compact size. [ABSTRACT FROM AUTHOR]

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- $\mu \text{m}$ technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective ${t}_{ox}$ value. [ABSTRACT FROM AUTHOR]