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In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18- $\mu \text{m}$ , 1-poly, and 4-metal CIS technology with a pixel array of $128 \times 160$ is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor $C_{\textit {FD}}$ on the floating diffusion node, which is remnant in VM. [ABSTRACT FROM AUTHOR]

This paper presents a mutual capacitive touch screen panel (TSP) readout IC (ROIC) with a differential continuous-mode parallel operation architecture (DCPA). The proposed architecture achieves a high product of signal-to-noise ratio (SNR) and frame rate, which is a requirement of ROIC for large-sized TSP. DCPA is accomplished by using the proposed differential sensing method with a parallel architecture in a continuous-mode. This architecture is implemented using a continuous-type transmitter for parallel signaling and a differential-architecture receiver. A continuous-type differential charge amplifier removes the common-mode noise component, and reduces the self-noise by the band-pass filtering effect of the continuous-mode charge amplifier. In addition, the differential parallel architecture cancels the timing skew problem caused by the continuous-mode parallel operation and effectively enhances the power spectrum density of the signal. The proposed ROIC was fabricated using a 0.18-$\mu$m CMOS process and occupied an active area of 1.25 \text{mm}^{2}. The proposed system achieved a 72 dB SNR and 240 Hz frame rate with a 32 channel TX by 10 channel RX mutual capacitive TSP. Moreover, the proposed differential-parallel architecture demonstrated higher immunity to lamp noise and display noise. The proposed system consumed 42.5 mW with a 3.3-V supply. [ABSTRACT FROM PUBLISHER]

Mismatch motivates many of the design decisions for binary weighted, ratiometric converters, such as successive approximation (SAR) analog-to-digital converters (ADC), but the statistical relationship between mismatch and signal-to-noise-plus-distortion ratio (SNDR) has not been precisely quantified. In this paper, we analyze the effects of capacitor mismatch in a binary weighted, charge redistribution SAR ADC and derive a new analytic expression relating capacitor mismatch and the effective-number-of-bits (ENOB). We then explore the statistics of this new expression and develop a model that accurately predicts yield in terms of ENOB. Finally, the major results of this paper are generalized into a simple and compact design equation that relates resolution, mismatch, and ENOB to yield for all binary weighted, ratiometric converters. The expressions derived in this paper offer practical insight into the relationship between mismatch and performance for all binary, weighted ratiometric converters with these results validated through numerical simulations. [ABSTRACT FROM PUBLISHER]

Conventional capacitance-to-digital converters (CDCs) suffer limitations either on narrow capacitance range or low resolution for jitter-induced noise and high power consumption. In order to avoid these limitations, a 13-b 1 pF–10 nF generic CDC is presented. In the proposed CDC with the oversampled $\Delta \Sigma $ modulation, the zero-crossing-based circuits (ZCBCs) are used to replace the operational transconductance amplifier to avoid feedback loop stability issues. However, the ZCBCs inevitably incur the non-idealities and thus, a novel calibration scheme is presented for efficient non-ideality-error cancellation. In addition, for the purpose of making the proposed CDC sufficiently intelligent to adapt to a wide capacitance-sensing range, an adaptive auto-range mechanism is proposed. The above three techniques complement each other and work as a whole leading to the proposed CDC with wide range, high resolution, high linearity, and low power consumption. A prototype fabricated using 0.18- $\mu \text{m}$ CMOS technology is experimentally verified using a MEMS capacitive humidity sensor. The measurement results show that the CDC achieves a 13-b root-mean-square noise equivalent resolution with a 128- $\mu \text{s}$ conversion time and a 230 fJ/conversion-step figure of merit. The calibration scheme enhances the linearity from 7 to 11.4 b in the 1 pF–10 nF compatible capacitance range. [ABSTRACT FROM AUTHOR]

A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3\,\times\,3 kernel. The proof-of-concept circuit is implemented in 0.35 \mum CMOS technology, and contains a 64\,\times\,64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 \muW per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s. [ABSTRACT FROM AUTHOR]

The stability of a stepwise waveform of an adiabatic charge recycling circuit with tank capacitors is investigated. We propose a new tank capacitor circuit with two-string capacitor arrays. We experimentally confirmed the stability of the five-step waveform from the tank capacitors. The voltage changes of tank capacitors in the experiment are consistent with the simulation. The power consumption is reduced to one-fifth due to the five-step waveform. We analyze the stability using matrix theory. The results prove that the step waveform is stable for any circuit topology. Moreover, we consider the effects of conductors fixed at a certain voltage and floating conductors and confirm the system is stable using matrix theory. [ABSTRACT FROM AUTHOR]

A successive approximation analog-to-digital converter (ADC) architecture is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. While targeting medium resolutions and speed, the threshold configuring (TC) ADC achieves low power consumption and small area occupation by using a fully dynamic configurable comparator and an asynchronous controller, with no need for a highly linear feedback D/A converter. The TC-ADC embeds its own references, and relies on a minimal amount of passive components or calibration loops. A 6-bit prototype implementation in 90-nm digital CMOS technology achieves 32-dB SNDR at 50 MS/s and consumes 240 μW from 1-V analog and 0.7-V digital supplies. This results in 150 fJ/conversion-step in a core area occupation of only 0.0055 mm . [ABSTRACT FROM AUTHOR]