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Mismatch motivates many of the design decisions for binary weighted, ratiometric converters, such as successive approximation (SAR) analog-to-digital converters (ADC), but the statistical relationship between mismatch and signal-to-noise-plus-distortion ratio (SNDR) has not been precisely quantified. In this paper, we analyze the effects of capacitor mismatch in a binary weighted, charge redistribution SAR ADC and derive a new analytic expression relating capacitor mismatch and the effective-number-of-bits (ENOB). We then explore the statistics of this new expression and develop a model that accurately predicts yield in terms of ENOB. Finally, the major results of this paper are generalized into a simple and compact design equation that relates resolution, mismatch, and ENOB to yield for all binary weighted, ratiometric converters. The expressions derived in this paper offer practical insight into the relationship between mismatch and performance for all binary, weighted ratiometric converters with these results validated through numerical simulations. [ABSTRACT FROM PUBLISHER]

As externally powered microsystems become more common, designers need better tools to understand power delivery systems such as non-resonant capacitive coupling. In this paper we present the first general method which allows a designer to easily model power delivery through capacitive coupling. The method uses a power iteration technique which allows one to analyze systems when the time to charge the coupling capacitor is longer than a charge cycle, enabling us to analyze a greater range of systems than previously possible. In fact, we are able to model the entire system with an equivalent resistance. We show that our model accurately reproduces both static and dynamic characteristics of the exact solution and that this model is general, in that it is valid for capacitor charge times that are longer as well as shorter than a charge cycle. This model also reveals several regions of operation where different parameters (e.g., capacitance, frequency and series resistance) dominate, allowing the designer to quickly and intuitively understand the design space for capacitive power transfer. [ABSTRACT FROM PUBLISHER]

Photovoltaic (PV) energy harvesting is commonly used to power autonomous devices, and maximum power point tracking (MPPT) is often used to optimize its efficiency. This paper describes an ultra low-power MPPT circuit with a novel sample-and-hold and cold-start arrangement, enabling MPPT across the range of light intensities found indoors, which has not been reported before. The circuit has been validated in practice and found to cold-start and operate from 100 lux (typical of dim indoor lighting) up to 5000 lux with a 55 cm2 amorphous silicon PV module. It is more efficient than non-MPPT circuits, which are the state-of-the-art for indoor PV systems. The proposed circuit maximizes the active time of the PV module by carrying out samples only once per minute. The MPPT control arrangement draws a quiescent current draw of only 8 μA, and does not require an additional light sensor as has been required by previously reported low-power MPPT circuits. [ABSTRACT FROM PUBLISHER]

The linearity of a high-resolution pipelined analog- to-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolation- based digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35 3.3 V CMOS process. The ADC samples at 20 MS/s. The calibration improves the ADC DNL and INL from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590 kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB respectively. The 11.8-ENOB 20 MS/s ADC consumes 56.3 mW power with 3.3 V supply. The 0.78 pJ/step figure-of-merit (FOM) is low for designs in 0.35 CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8 dB due to the slow settling of the first pipeline stage. [ABSTRACT FROM PUBLISHER]

A general transposed series-parallel topology of a switched-capacitor converter is presented and analyzed in this paper. This topology evolved from the conventional series-parallel through rectangular matrices based topologies to partial arbitrary matrices which are constructed of different size strings of capacitors to arbitrary matrices, based on a bank of equally valued capacitors. Theoretically, these topologies have a large number of dc/dc voltage ratios, which lead to the capability to achieve very accurate fixed dc/dc voltage ratios. These topologies also have the capability for “fine tuning” when voltage regulation is necessary. For the general transposed series-parallel topology, it is shown that the number of possible dc/dc voltage transfer ratios escalates exponentially with an addition of each capacitor as the sum of partition functions. Therefore, relatively fewer components are required for an assumed accurate voltage ratio. Dispersion of parameters in the capacitance value is considered. Small ripple analysis, losses calculations and efficiency considerations are also discussed. Simulations are performed for 2.2 and 2.25 voltage ratios. The simulations are in good agreement with the theoretical calculations. [ABSTRACT FROM PUBLISHER]

In this paper, two novel negative impedance converter (NIC) structures are proposed. One of the introduced NICs exhibits the property of both simultaneously reduced nonideal gain and parasitic impedance effects. Also, the other one shows the property of reducing only parasitic impedance effects and employs only second-generation current conveyors; accordingly, it can be realized with commercially available active devices such as AD844s. In order to show the performance of the introduced NICs, a versatile circuit employing a minimum number of active and passive elements for all the analog filters and lossy inductor simulators is developed. The proposed topology with appropriate component and input port selections gives four kinds of lossy grounded simulated inductors as well. Further, the presented multipurpose circuit is the first one that provides both of the current-mode and voltage-mode standard universal filter responses as well as synthetic inductors from the same topology. The developed topology employing only grounded capacitors can also realize transimpedance-mode low-pass and bandpass responses simultaneously; thus, it is convenient for integrated circuit (IC) realization. Likewise, positive lossy inductor simulators consist of a grounded capacitor. Nevertheless, the realized circuit requires a single resistive component-matching condition. Simulation results using SPICE program and experimental results are included to verify the theoretical ones. [ABSTRACT FROM AUTHOR]

Jump resonance is a phenomenon where smooth changes in the input of a nonlinear filter lead to abrupt changes in its output. For over 50 years, research has defined the region of operation where jump resonance can occur so that this region may be avoided by limiting the signal amplitude of operation. This paper provides an intuitive understanding of jump resonance and predicts the behavior of the system in the jump resonance regime. This allows for further tradeoffs between system behavior and power consumption for highly power-efficient filtering systems. Our technique is verified against experimental data. Then we present a system that gracefully adapts its quality factor, avoiding jump resonance in a way qualitatively similar to biology. Finally, we demonstrate an integrated circuit realization. [ABSTRACT FROM AUTHOR]

Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter. [ABSTRACT FROM AUTHOR]

Conventional capacitance-to-digital converters (CDCs) suffer limitations either on narrow capacitance range or low resolution for jitter-induced noise and high power consumption. In order to avoid these limitations, a 13-b 1 pF–10 nF generic CDC is presented. In the proposed CDC with the oversampled $\Delta \Sigma $ modulation, the zero-crossing-based circuits (ZCBCs) are used to replace the operational transconductance amplifier to avoid feedback loop stability issues. However, the ZCBCs inevitably incur the non-idealities and thus, a novel calibration scheme is presented for efficient non-ideality-error cancellation. In addition, for the purpose of making the proposed CDC sufficiently intelligent to adapt to a wide capacitance-sensing range, an adaptive auto-range mechanism is proposed. The above three techniques complement each other and work as a whole leading to the proposed CDC with wide range, high resolution, high linearity, and low power consumption. A prototype fabricated using 0.18- $\mu \text{m}$ CMOS technology is experimentally verified using a MEMS capacitive humidity sensor. The measurement results show that the CDC achieves a 13-b root-mean-square noise equivalent resolution with a 128- $\mu \text{s}$ conversion time and a 230 fJ/conversion-step figure of merit. The calibration scheme enhances the linearity from 7 to 11.4 b in the 1 pF–10 nF compatible capacitance range. [ABSTRACT FROM AUTHOR]

Online adaptive equalization is proposed to calibrate channel mismatch errors in time-interleaved (TI) analog-to-digital converter (ADC) arrays with a linear reference path. Code-domain filters are shown to be effective in removing interchannel as well as intrachannel nonlinearity and mismatch errors, including offset, gain, and differential nonlinearity (DNL) and integral nonlinearity (INL) mismatches. An 8-bit, 600-MS/s, 0.13- μm CMOS prototype measured a signal-to-noise plus distortion ratio (SNDR) of 31.0/47.4 dB, a spurious-free dynamic range (SFDR) of 32.8/63.6 dB, a DNL of 1.30/0.30 LSBs, and an INL of 1.70/0.23 LSBs in lab testing without/with equalization, respectively. [ABSTRACT FROM PUBLISHER]

Presented is a design of a mixed signal integrator, consisting of a traditional analog integrator (op-amp with capacitor in feedback) augmented with comparators, logic, counter registers, and a precharged capacitor that can be switched into, and out of, the input of the analog integrator. This device integrates with analog, but stores results in analog and digital. Whenever an analog integrator voltage equals or exceeds a threshold voltage, an amount of charge equivalent to the threshold voltage is cleared from the feedback capacitor of the analog integrator, and the counter register is incremented or decremented accordingly. With the threshold voltage representing one in a counting system, these actions convert the integrator contents to ±1. At any instant, the counter register holds the integer portion of the integral, and the analog integrator holds any fractional portion, permitting the integral to be internally stored as a real number. The mixed signal integrator accumulates integral beyond supply rails without op-amp saturation; has analog integrator bandwidth that extends into the limited gain low frequency region; avoids drift due to low pass filter effects and unbalanced input biases; and exhibits no sampled data or discrete system effects. Tests on a PCB prototype verified the design. [ABSTRACT FROM PUBLISHER]

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 \mu \m 1.2 V standard CMOS technology are shown. [ABSTRACT FROM PUBLISHER]

Noise analysis for comparator-based circuits is presented. The goal is to gain insight into the different sources of noise in these circuits for design purposes. After the general analysis techniques are established, they are applied to different noise sources in the comparator-based switched-capacitor pipeline analog-to-digital converter (ADC). The results show that the noise from the virtual ground threshold detection comparator dominates the overall ADC noise performance. The noise from the charging current can also be significant, depending on the size of the capacitors used, but the contribution was small in the prototype. The other noise sources have contributions comparable to those in op-amp-based designs, and their effects can be managed through appropriate design. In the prototype, folded flicker noise was found to be a significant contributor to the broadband noise because the flicker noise of the comparator extends beyond the Nyquist rate of the converter. [ABSTRACT FROM AUTHOR]

We present for the first time, a fully integrated battery powered RFID integrated circuit (IC) for operation at ultra- high frequency (UHF) and microwave bands. The battery powered RFID IC can also work as a passive RFID tag without a battery or when the battery has died (i.e., voltage has dropped below 1.3 V); this novel dual passive and battery operation allays one of the major drawbacks of currently available active tags, namely that the tag cannot be used once the battery has died. When powered by a battery, the current consumption is 700 nA at 1.5 V (400 nA if internal signals are not brought out on testpads). This ultra-low-power consumption permits the use of a very small capacity battery of 100 mA·hr for lifetimes exceeding ten years; as a result a battery tag that is very close to a passive tag both in form factor and cost is made possible. The chip is built on a 1-µm digital CMOS process with dual poly layers, EEPROM and Schottky diodes. The RF threshold power at 2.45 GHz is -19 dBm which is the lowest ever reported threshold power for RFID tags and has a range exceeding 3.5 m under FCC unlicensed operation at the 2.4-GHz microwave band. The low threshold is achieved with architectural choices and low-power circuit design techniques. At 915 MHz, based on the experimentally measured tag impedance (92-j837) and the threshold spec of the tag (200 mV), the theoretical minimum range is 24 m. The tag initially is in a "low-power" mode to conserve power and when issued the appropriate command, it operates in "full-power" mode. The chip has on-chip voltage regulators, clock and data recovery circuits, EEPROM and a digital state machine that implements the ISO 18000-4 B protocol in the "full-power" mode. We provide detailed explanation of the clock recovery circuits and the implementation of the binary sort algorithm, which includes a pseudorandom number generator. Other than the antenna board and a battery, no external components are used. [ABSTRACT FROM AUTHOR]