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The generalized method of time and transfer constants is introduced. It can be used to determine the transfer function to the desired level of accuracy in terms of time and transfer constants of first-order systems using exclusively low frequency calculations. This method can be used to determine the poles and zeros of circuits with both inductors and capacitors. An inductive proof of this generalized method is given which subsumes special cases, such as methods of zero- and infinite-value time constants. Several important and useful corollaries of this method are discussed and several examples are analyzed. [ABSTRACT FROM AUTHOR]

Noise analysis for comparator-based circuits is presented. The goal is to gain insight into the different sources of noise in these circuits for design purposes. After the general analysis techniques are established, they are applied to different noise sources in the comparator-based switched-capacitor pipeline analog-to-digital converter (ADC). The results show that the noise from the virtual ground threshold detection comparator dominates the overall ADC noise performance. The noise from the charging current can also be significant, depending on the size of the capacitors used, but the contribution was small in the prototype. The other noise sources have contributions comparable to those in op-amp-based designs, and their effects can be managed through appropriate design. In the prototype, folded flicker noise was found to be a significant contributor to the broadband noise because the flicker noise of the comparator extends beyond the Nyquist rate of the converter. [ABSTRACT FROM AUTHOR]

An integrated circuit (IC) design for low and high side gate drive in high-voltage applications is presented based on use of two identical low-voltage ICs that provide a low cost alternative to existing high-voltage IC floating gate drivers. The approach uses a single external coupling capacitor between the two ICs with on-chip circuitry to provide charge pump power supply and on/off signaling. Design details are given for each of the core blocks of a custom IC prototype fabricated in a 20-V 0.8-µm CMOS process. Experimental results are presented demonstrating successful drive of a 200-V half-bridge with an electronic ballast and 32-W linear fluorescent lamp load. [ABSTRACT FROM AUTHOR]

We present for the first time, a fully integrated battery powered RFID integrated circuit (IC) for operation at ultra- high frequency (UHF) and microwave bands. The battery powered RFID IC can also work as a passive RFID tag without a battery or when the battery has died (i.e., voltage has dropped below 1.3 V); this novel dual passive and battery operation allays one of the major drawbacks of currently available active tags, namely that the tag cannot be used once the battery has died. When powered by a battery, the current consumption is 700 nA at 1.5 V (400 nA if internal signals are not brought out on testpads). This ultra-low-power consumption permits the use of a very small capacity battery of 100 mA·hr for lifetimes exceeding ten years; as a result a battery tag that is very close to a passive tag both in form factor and cost is made possible. The chip is built on a 1-µm digital CMOS process with dual poly layers, EEPROM and Schottky diodes. The RF threshold power at 2.45 GHz is -19 dBm which is the lowest ever reported threshold power for RFID tags and has a range exceeding 3.5 m under FCC unlicensed operation at the 2.4-GHz microwave band. The low threshold is achieved with architectural choices and low-power circuit design techniques. At 915 MHz, based on the experimentally measured tag impedance (92-j837) and the threshold spec of the tag (200 mV), the theoretical minimum range is 24 m. The tag initially is in a "low-power" mode to conserve power and when issued the appropriate command, it operates in "full-power" mode. The chip has on-chip voltage regulators, clock and data recovery circuits, EEPROM and a digital state machine that implements the ISO 18000-4 B protocol in the "full-power" mode. We provide detailed explanation of the clock recovery circuits and the implementation of the binary sort algorithm, which includes a pseudorandom number generator. Other than the antenna board and a battery, no external components are used. [ABSTRACT FROM AUTHOR]

The difficulties encountered in matching an antenna to its optimal impedance are reduced with an adaptive 0.35-μm CMOS circuit based on several switched shunt capacitors arranged in capacitor banks and on a few external series inductors. As high-quality inductors are difficult to obtain in CMOS, the inductors are placed either in an low-temperature cofired ceramic (LTCC) substrate or is a lumped component outside the core circuit. The circuits, presented here through a range of simulations, are optimized to function within the ISM 2.4-GHz band, but the general approach employed to improve matching can be used for other frequency bands as well. The circuits discussed provide a VSWR ≤ 2 match for every impedance with VSWR ≤ 5. There is a 1-dB power Loss for a perfect 50 Ω → 50 Ω transformation, a break-even point at VSWR = 1.5, and a 3-dB increase in delivered power for VSWR = 4.3. [ABSTRACT FROM AUTHOR]