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Accurate modeling of magnetic tunnel junction (MTJ) is critical for design of memories such as spin-transfer-torque magnetoresistive random access memory (STT-MRAM) and spin logic circuits such as spin flip flops. This paper reviews several static and dynamic models for the MTJ and compares them for their capabilities and limitations. Furthermore, a Verilog-A model is developed to predict dynamic characteristics of the MTJ. These models are used in simulating a prototype circuit to illustrate their strengths and weaknesses. [ABSTRACT FROM AUTHOR]

Dynamic average-value models (AVMs) for AC-DC rectifier circuits are generally formulated in state-space form and hence are straightforward to implement in state-variable-based simulation languages. In the nodal analysis-based approach used in electromagnetic transient (EMTP-type) simulation packages, the development of AVMs requires additional effort to reformulate and interface the models with the external ac and dc networks. This paper proposes a new averaged-circuit model for three-phase line-commutated rectifiers which is directly interfaced with the ac and dc networks, thereby achieving a simultaneous solution of the respective variables in EMTP-type solution. The proposed model is verified against conventionally interfaced model, as well as detailed switching model of the original rectifier circuit. A significant improvement of numerical accuracy and stability of the solution is demonstrated even at fairly large time steps. [ABSTRACT FROM AUTHOR]

The harmonic signal rejection capability and the rejection schemes of polyphase downconverters are discussed. An analysis of a simple model of a polyphase downconverter shows that n-phase converter can reject up to (n-2)th harmonic signal, and that (n-1)th harmonic signal aliases into the desired signal. It means that the harmonic rejection is not exclusive ability of downconverters with large number of phases, and conventional downconverters with fewer phases have the ability. An example is a differential amplifier type downconverter (n=2), which has the ability of even harmonic signal rejection as common-mode signal. In this paper, the common-mode concept is extended to polyphase circuits. It is named “partial common mode,” because it does not have to be common for all node but is common for a part of nodes. The partial common-mode rejection is effective for harmonic rejection. There is the other type of harmonic rejection techniques for polyphase downconverters, i.e., signal weighting-and-summing type. Comparison between the harmonic rejection with weighting-and-summing circuit and that with the common-mode rejection circuit is discussed, too. Due to its simple structure, a 6-phase downconverter with partial common-mode rejection is attractive for practical wideband receivers. [ABSTRACT FROM PUBLISHER]

A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models. [ABSTRACT FROM AUTHOR]