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The pervasiveness of IoT and embedded devices allows the deployment of services that were unthinkable only few years ago. Such devices are typically small, run unattended, possibly on batteries and need to have a low cost of production. As all software systems, this type of devices need to be updated for different reasons, e.g., introducing new features, improving/correcting existing functionalities or fixing security flaws. At the same time, because of their low-complexity, standard software distribution platforms and techniques cannot be used to update the software. In this paper we review the current limitations posed to software distribution systems for embedded/IoT devices, consider challenges that the researchers in this area have been identifying and propose the corresponding solutions. [ABSTRACT FROM AUTHOR]

This paper aims to show that it is possible to improve security for over the air update functionalities in an automotive scenario through the use of a cryptographic scheme, called "Attribute-Based-Encryption" (ABE), which grants confidentiality to the software/firmware update done Over The Air (OTA). We demonstrate that ABE is seamlessly integrable into the state of the art solutions regarding the OTA update by showing that the overhead of the ABE integration in terms of computation time and its storage is negligible w.r.t. the other overheads that are introduced by the OTA process, also proving that security can be enhanced with a minimum cost. In order to support our claim, we report the experimental results of an implementation of the proposed ABE OTA technique on a Xilinx ZCU102 evaluation board, which is an automotive-oriented HW/SW platform that is equipped with a Zynq UltraScale+ MPSoC chip that is representative of the computing capability of real automotive Electronic Control Units (ECUs). [ABSTRACT FROM AUTHOR]

Abstract The Internet of Things (IoT) offers a vast infrastructure of numerous interconnected devices capable of communicating and exchanging data. Pervasive computing applications can be formulated on top of the IoT involving nodes that can interact with their environment and perform various processing tasks. Any task is part of intelligent services executed in nodes or the back end infrastructure for supporting end users' applications. In this setting, one can identify the need for applying updates in the software/firmware of the autonomous nodes. Updates are extensions or patches significant for the efficient functioning of nodes. Legacy methodologies deal with centralized approaches where complex protocols are adopted to support the distribution of the updates in the entire network. In this paper, we depart from the relevant literature and propose a distributed model where each node is responsible to, independently, initiate and conclude the update process. Nodes monitor a set of metrics related to their load and the performance of the network and through a time-optimized scheme identify the appropriate time to conclude the update process. We report on an infinite horizon optimal stopping model on top of the collected performance data. The aim is to make nodes capable of identifying when their performance and the performance of the network are of high quality to efficiently conclude the update process. We provide specific formulations and the analysis of the problem while extensive simulations and a comparison assessment reveal the advantages of the proposed solution. Highlights • We propose an time optimized, performance-aware scheme for software updates management. • The mechanism decides when an update process should be activated. • We offer a method for deriving the optimal time for initiating the update process. • With the proposed mechanism, IoT nodes enjoy the best possible performance. • We offer extensive simulations and an analysis of the results. [ABSTRACT FROM AUTHOR]

Superior availability is one of the outstanding features of modern zSeries® machines, among the most highly rated of any existing computer platforms in this reqard. Many features contribute to this characteristic, some in hardware, some in software. This paper describes the first error data capture (FEDC) concept in the zSeries 990. The concept is used for both zSeries integration efficiency and its ability to gain field data for problem determination in the user environment. FEDC is not a single function, but part of all internal software (firmware) in the z990. This paper explains the overall concept and implementation details of the various internal functional layers (subsystems). [ABSTRACT FROM AUTHOR]

For two decades, large parts of zSeries® firmware have been written in the PL8 programming language. The existence of a large amount of mature zSeries firmware source code and our excellent experience with PL8 for system programming suggest keeping this language. However, the firmware address space of today's zSeries servers may exceed 2 GB, raising the need for a new 64-bit PL8 compiler, since the original implementation, developed at the IBM Thomas J. Watson Research Center, Yorktown Heights, New York, supports only 32-bit platforms. The GNU compiler collection (GCC) (GNU is a freeware UNIX® -like operating system) has been used to translate those parts of firmware written in C for some years and has also proved successful in compiling Linux™ for zSeries. This fact, combined with the highly modular GCC design,suggested reimplementing PL8 within the GCC framework. In this paper, we report on the extension of PL8 to support 64-bit addressing, its implementation as a GCC front end, and the validation of the new compiler. We also evaluate PL8 as a language for highly reliable low-level programming and give some performance data. The paper documents the high level of quality achieved by the GCC open-source project and how such software fits into the traditional IBM software development processes. [ABSTRACT FROM AUTHOR]

Software-defined radio (SDR) research deals with a mixture of hardware and software technologies, where RF operating parameters and components are to be set or altered by modifiable software or firmware. This paper describes the coarse-grained reconfigurable array (CGRA) implementations of SDR architecture. This architecture is an extension of traditional SDR in complex adaptation strategies, such as highly reliable communications and efficient utilization of the resources and spectrum upgrade, through its internal states (performance) and hardware architecture. The proposed CGRA-based SDR implementation is based on dynamic partial reconfiguration methodology, which has the capability of reusing the same hardware module to handle different algorithms. This CGRA-based SDR provides greater flexibility and adds new abilities without additional cost. Initially, the SDR system was simulated in the Agilent SystemVue environment to analyze the error boundaries of the proposed SDR architecture. Then the SDR system was coded in the Verilog hardware description language and implemented on top of CGRAs such as the MOLEN, MORPHOSYS, and ADRES reconfigurable system-on-chip (SoC) architectures. These SoC architectures were installed within the Xilinx Virtex 5 field-programmable gate array to analyze the performance of SDR architectures in terms of area utilization, operational speed, power optimization, reconfiguration time, coprocessor execution time, preemption support, and relocation support of the system. The performance analysis indicates that the ADRES SoC architecture is suitable for dynamic partial reconfiguration and the MOLEN SoC architecture is more suitable for power, area, and speed requirements and low circuit complexity compared to other architectures. [ABSTRACT FROM AUTHOR]

The need for an increasingly dynamic and more cost-efficient data-center infrastructure has led to the adoption of a software defined model that is characterized by: the creation of a federated control plane to judiciously allocate and control appropriate heterogeneous infrastructure resources in an automated fashion, the ability for applications to specify criteria, such as performance, capacity, and service levels, without detailed knowledge of the underlying infrastructure; and the migration of data-plane capabilities previously embodied as purpose-built devices or firmware into software running on a standard operating systems in commercial off-the-shelf servers. This last trend of hardware-based capabilities migrating to software is enabling yet another shift to hyperconvergence, which refers to merger of traditionally separate networking, compute, and storage capabilities in integrated system software. This paper examines the convergence of the software defined infrastructure stack, and introduces a hyperconverged compute and storage architecture, in which the IBM General Parallel File System (GPFSA) implements the software defined data plane that dynamically supports workloads ranging from high-I/O virtual desktop infrastructure applications to more compute-oriented analytics applications. The performance and scalability characteristics of this architecture are evaluated with a prototype implementation. [ABSTRACT FROM AUTHOR]

Abstract: Forthcoming hardware upgrades to the CMS experiment trigger and readout system are based upon the ATCA or μTCA bus standards, giving them the opportunity to be controlled via commodity gigabit Ethernet. These hardware upgrades supersede existing systems largely based upon the VME-bus standard, and thus a requirement has arisen to provide a new low-level control infrastructure for use by trigger and readout subsystem developers. This paper details the recent research and development into a tightly-integrated suite of software and firmware based upon the IPbus protocol that allows such Ethernet-attached hardware to be controlled in an efficient and highly-scalable manner. [Copyright &y& Elsevier]

While a number of techniques to further improve firmware quality and design stability and to reduce firmware field problems over the long term were introduced with the IBM z900 and z990, a second wave of techniques were introduced for the IBM System z10™ platform. This paper describes the three new techniques: an enhanced static code analysis tool, code coverage, and simulation improvements. [ABSTRACT FROM AUTHOR]

In this paper we describe Bare Metal Linux (BML), a cut-down version of Linux® 2.6 that requires no firmware, has an in-memory root file system, and runs without a virtualization layer. We designed and implemented BML in order to accelerate the bring up of POWER5™-based systems. The use of BML allows testing and validation of the POWER5-based system to be conducted in parallel with the standard path, which involves the bring up of a hypervisor, the partition firmware, and the operating system. BML, which has fast boot times and can be modified quickly, is used in fault detection during chip manufacturing, POWER5 chip verification, system-board verification, and benchmarking for performance. BML is also used to reproduce and resolve problems in Linux. [ABSTRACT FROM AUTHOR]

Secure firmware update is an important stage in the Internet of Things (IoT) device life-cycle. Prior techniques, designed for other computational settings, are not readily suitable for IoT devices, since they do not consider idiosyncrasies of a realistic large-scale IoT deployment. This motivates our design of architecture for secure software update of realistic embedded devices (ASSURED), a secure and scalable update framework for IoT. ASSURED includes all stakeholders in a typical IoT update ecosystem, while providing end-to-end security between manufacturers and devices. To demonstrate its feasibility and practicality, ASSURED is instantiated and experimentally evaluated on two commodity hardware platforms. Results show that ASSURED is considerably faster than current update mechanisms in realistic settings. [ABSTRACT FROM AUTHOR]

Discusses issues related to complexity regulation and firmware or software efficiency for a hybrid video codec. Examples of existing or potential video-coding applications; Introduction of the standardized techniques for hybrid video coding; Categories of modules in a video codec.