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Flash memory is featured with salient advantages over conventional hard disks for massive data storage and efficient on-board data processing. A flash translation layer (FTL) is a critical component for flash-based storage devices to handle particular technical constraints of flash. It is desirable to use flash memory for the storage of massive remote sensing images and support on-board remote sensing data processing applications, which typically require high I/O performance and hence call for advanced FTL design and implementations. In this paper, we introduce our efforts in developing a reinforcement learning driven page-level mapping and caching scheme (named Q-FTL) that is adaptive and responsive to ever-changing I/O streams of on-board remote sensing image processing operations. The adaptability and responsiveness are achieved by the separation of large and small I/O requests, an integrated weighting scheme to measure access costs of cached translation pages, and a reinforcement learning driven cache replacement algorithm. We demonstrate the efficiency of the proposed approach using actual I/O traces generated from on-board remote sensing image processing applications. Experimental results show that Q-FTL improves over several current state-of-the-art FTLs by a large margin and even achieves competitive performance close to an idealized pure page mapping FTL in some cases. [ABSTRACT FROM AUTHOR]

To mitigate the long write latency of NAND flash memory, solid-state drives (SSDs) typically use capacitor-powered SRAM or DRAM to realize internal nonvolatile write buffering. Due to the cost and size constraints, intra-SSD capacitors can only power a very small amount (e.g., 8 MB or 16 MB) of nonvolatile write buffer. As a result, most commercial SSDs simply use the few MBs of capacitor-powered write buffer in the first-in first-out (FIFO) manner without employing any advanced data eviction policy. This paper presents a set of design strategies across the application and storage device levels that can effectively leverage the very small intra-SSD write buffer to noticeably reduce the amount of data being physically written to NAND flash memory. These cross-layer design strategies are primarily geared towards mainstream applications (e.g., database and filesystem) that heavily involve logging/journaling operations. This paper discusses different strategies for realizing flash memory write traffic reduction through nominal application-level modifications, and presents solutions to accordingly manage the write buffer at small processing and memory resource usage inside SSDs. To evaluate the potential effectiveness, we carried out case studies based upon popular open-source relational databases and filesystem. With only 8 MB of intra-SSD capacitor-powered write buffer, our experimental results show that the developed design solutions can reduce up to 39.7, 36.5, and 52.9 percent of total NAND flash memory write traffic for MySQL, ext4, and PostgreSQL, respectively. [ABSTRACT FROM AUTHOR]

Multi-level per cell (MLC) technique has been widely used to improve the storage density of NAND flash memory. In current design practice, bits stored in one cell are mapped to different pages, and all pages are protected with the same error correction code (ECC). However, those bits in one MLC flash memory cell have different error rates, and such unbalance increases with the number of bits in one cell. To guarantee the storage integrity, ECC should be tuned to cover the worst case page, which results in over-protection and redundancy waste for other pages and hence reduces storage capacity. This bit-to-cell mapping scheme also limit the number of bits in one cell to be integer. This paper proposes an aggregated page programming scheme, which maps all bits in one cell into the same page, to balance all pages to experience the same but lower overall bit error rates, so that the weaker ECC with higher coding rate can be employed. Furthermore, the noise margin of NAND flash memory cell decreases with program/erase cycling. To exploit such noise margin dynamics, this paper proposes to accommodate more storage levels in one cell during its early lifetime and dynamically modulate the number of storage levels to increase the overall effective storage capacity. Not-a-power-of-2 storage levels in one cell should be used to exploit the storage capacity aggressively, which can be enabled through proposed aggregated page programming scheme. Simulation results show the program capacity can be increased by more than 50 %. [ABSTRACT FROM AUTHOR]

This paper presents a cross-layer design strategy to reduce SSD response time and its variation. The key is to cohesively exploit system-level run-time data access workload variation and temporal locality and device-level NAND flash memory write latency versus data retention time trade-off. The basic idea is simple: once write intensity of the workload increases and begins to degrade SSD response time, we speed up memory programming at the penalty of shorter data retention time, and rewrite these short-lifetime data later, if necessary, when workload write intensity drops. A scheduling solution is developed to effectively implement this design strategy. Simulations over various workloads were carried out and the results demonstrate that the cross-layer design strategy can reduce the average SSD response time by up to 52.3%. [ABSTRACT FROM AUTHOR]

Future flash-based solid-state drives (SSDs) must employ increasingly powerful error correction code (ECC) and digital signal processing (DSP) techniques to compensate the negative impact of technology scaling on NAND flash memory device reliability. Currently, all the ECC and DSP functions are implemented in a central SSD controller. However, the use of more powerful ECC and DSP makes such design practice subject to significant speed performance degradation and complicated controller implementation. An EZ-NAND (Error Zero NAND) flash memory design strategy is emerging in the industry, which moves all the ECC and DSP functions to each memory chip. Although EZ-NAND flash can simplify controller design and achieve high system speed performance, its high silicon cost may not be affordable for large-capacity SSDs in computing systems. We propose a quasi-EZ-NAND design strategy that hierarchically distributes ECC and DSP functions on both NAND flash memory chips and the central SSD controller. Compared with EZ-NAND design concept, it can maintain almost the same speed performance while reducing silicon cost overhead. Assuming the use of low-density parity-check (LDPC) code and postcompensation DSP technique, trace-based simulations show that SSDs using quasi-EZ-NAND flash can realize almost the same speed as SSDs using EZ-NAND flash, and both can reduce the average SSD response time by over 90 percent compared with conventional design practice. Silicon design at 65 nm node shows that quasi-EZ-NAND can reduce the silicon cost overhead by up to 44 percent compared with EZ-NAND. [ABSTRACT FROM AUTHOR]

Lossless data compression for data storage has become less popular as mass data storage systems are becoming increasingly cheap. This leaves many files stored on mass data storage media uncompressed although they are losslessly compressible. This paper proposes to exploit the lossless compressibility of those files to improve the underlying storage system performance metrics such as energy efficiency and access speed, other than saving storage space as in conventional practice. The key idea is to apply runtime lossless data compression to enable an opportunistic use of a stronger error correction code (ECC) with more coding redundancy in data storage systems, and trade such opportunistic extra error correction capability to improve other system performance metrics in the runtime. Since data storage is typically realized in the unit of equal-sized sectors (e.g., 512 B or 4 KB user data per sector), we only apply this strategy to each individual sector independently in order to be completely transparent to the firmware, operating systems, and users. Using low-density parity check (LDPC) code as ECC in storage systems, this paper quantitatively studies the effectiveness of this design strategy in both hard disk drives and NAND flash memories. For hard disk drives, we use this design strategy to reduce average hard disk drive read channel signal processing energy consumption, and results show that up to 38 percent read channel energy saving can be achieved. For NAND flash memories, we use this design strategy to improve average NAND flash memory write speed, and results show that up to 36 percent write speed improvement can be achieved for 2 bits/cell NAND flash memories. [ABSTRACT FROM AUTHOR]