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In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved according to the sparse spiking and non-uniform traffic of SNN. In this paper, we propose a 5.28-mm $^{2}~4096$ -neuron 1M-synapse energy-efficient digital SNN hardware that can achieve ultra-low energy per synaptic operation of 4.5 pJ. The proposed neuron computing unit is implemented in pipeline architecture to achieve high synaptic processing speed. The proposed spike processing unit can significantly increase the processing speed of the neuron core by $1.9\times $ and $9.4\times $ when the spike injection rate is 50% and 10%, respectively. Besides, the increase in the processing speed of the neuron core leads to a reduction in energy consumption of up to 81.5%. An event-driven clock gating circuit that can reduce the power consumption of the proposed neuron block by more than 70% is proposed in this paper. This paper proposes a supervised STDP+ algorithm for SNN training, and the classification accuracy of the MNIST digits is 89.6% with 73.6% weight sparsity of the output layer. [ABSTRACT FROM AUTHOR]

The design of a 12.77-MHz on-chip RC relaxation oscillator with digital compensation technique is presented. To maintain the frequency stability versus temperature and supply voltage variations, loop delay tuning by a digital feedback loop is developed in this system. In order to generate an on-chip reference for digital calibration, a replica comparator is added. The on-chip relaxation oscillator is fabricated in 0.18-\mu\textm CMOS process. The measured output frequency variation is 31 ppm/°C across −30 to 120 °C temperature range after compensation. The frequency variation over the supply voltage from 0.6 V to 1.1 V is ±0.5%/V. The measured total power consumption is 56.2 \mu\textW at 0.9-V supply voltage when the digital compensation blocks are enabled. After digital compensation, the compensation blocks can be shutdown for power saving, and the main oscillator consumes only 12.8 \mu\textW. [ABSTRACT FROM PUBLISHER]

With the advent of technology over the recent years, the low-density parity-check (LDPC) codes, which were once seen as an impractical concept, are now poised to be the next big thing in the communication standards of today for their near-capacity performances. Nonetheless, the physical implementation of LDPC decoders is more often than not encumbered by the arithmetic of its decoding algorithm. Entangled by numerous computations of minima, LDPC decoders not only require considerable amount of resources to the implement cascaded pair-wise comparators, but also yield low decoding throughputs. In this paper, we propound a novel design for the computation of minimum and subminimum in LDPC decoding, known as the cognitive-amplification detector (CAD). By leveraging on the finite precision of fixed-point binary representation in actual hardware, our CAD proposition renders significant gains in decoding throughput and savings in resource consumption of up to 20% and 15%, respectively, not to mention negligible trade-offs in error-correcting capabilities. [ABSTRACT FROM AUTHOR]

This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rd-order harmonic distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal, compared to AD-modulated designs. [ABSTRACT FROM PUBLISHER]

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 \muVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-\mu\ m standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems. [ABSTRACT FROM PUBLISHER]