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The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line scheme to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-kb 4-T SRAM is measured to consume 0.32 mW in the standby mode, and a 3.8-ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz. [ABSTRACT FROM AUTHOR]

Several letters to the editor are presented that deal with various topics including the Spring Festival which is considered the largest annual migration in China, a description of a local snack called Lamp Cakes, and thoughts on the 2012 doomsday theory.