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This paper presents a dynamic timing control technique to prevent timing errors in a pipeline under variations. Timing errors in a pipeline are prevented by borrowing time from the following stage and resolving the borrowed time by stretching the next clock cycle. This paper analyzes the operating principles of the proposed technique; presents the design of the required circuit components; and demonstrates its operation through fabrication and measurement of a prototype test-chip designed in an 180 nm CMOS process. The measurement results demonstrate that a system employing the dynamic timing control technique can operate in a wider frequency and voltage range. [ABSTRACT FROM AUTHOR]

Tolerating timing error due to power supply noise (PSN) in digital circuits can be done with adding voltage margins. Conservative addition of voltage margins leads wastes of power reducing the battery life in Internet of Things (IoT) devices. This paper aims to provide guidelines to avoid over-design due to PSN especially for the low-cost IoT devices. To this end, we first present an accurate time-domain behavioral model of timing slack variation due to PSN accounting for the clock-data compensation. The accuracy of the model is verified against SPICE for complex designs, including AES engine and LEON3 processor. To prove the effectiveness of our model for reducing voltage margin, we utilize our model in standard VLSI design flow for various examples, such as timing slack versus noise frequency analysis, determining optimal value of an on-die capacitor, analyzing the effects of time borrowing technique, and PVT variation simulations. The analysis shows that the model helps reduce pessimism in estimated timing slack. [ABSTRACT FROM PUBLISHER]

This paper presents a single-chip image sensor node with energy harvesting from the pixel array. The design includes a $128 \times 96$ pixel array that can be reconfigured to form an on-chip photovoltaic cell to harvest energy. An on-chip power management unit harvests energy from the pixel array, and delivers multiple regulated output voltage domains to power the sensor, image processor, and memory. The image processor is a low-overhead moving object detection unit to reduce the volume of transmitted data. The proposed sensor node is implemented on a single die in 130-nm technology. The pixel array demonstrates the peak harvested power of 2.1\mu \text{W} . The power dissipation of sensor is reduced by utilizing low-power circuit techniques, including block-level pipelining, power gating, and low-voltage memory. The system can be self-powered to process a frame at every 7 s. We discuss design approaches for improving the self-power performance. The noise characteristic of the reconfigurable sensor is analyzed, and the need for noise-robust moving object detection is evaluated for better image quality and improved self-power performance. [ABSTRACT FROM PUBLISHER]