Search

The advent of Transformers has revolutionized computer vision, offering a powerful alternative to convolutional neural networks (CNNs), especially with the local attention mechanism that excels at capturing local structures within the input and achieve state-of-the-art performance. Processing in-memory (PIM) architecture offers extensive parallelism, low data movement costs, and scalable memory bandwidth, making it a promising solution to accelerate Transformer with memory-intensive operations. However, the crucial issue lies in efficiently deploying an entire model onto resource-limited PIM system while parallelizing each transformer block with potentially many computational branches based on local-attention mechanisms. We present Allspark, which focuses on workload orchestration for visual Transformers on PIM systems, aiming at minimizing inference latency. Firstly, to fully utilize the massive parallelism of PIM, Allspark employs a fine-grained partitioning scheme for computational branches, and formats a systematic layout and interleaved dataflow with maximized data locality and reduced data movement. Secondly, Allspark formulates the scheduling of the complete model on a resource-limited distributed PIM system as an integer linear programming (ILP) problem. Thirdly, as local-global data interactions exhibit complex yet regular dependencies, Allspark provides a two-stage placement method, which simplifies the challenging placement of computational branches on the PIM system into the structured layout and greedy-based binding, to minimize NoC communication costs. Extensive experiments on 3D-stacked DRAM-based PIM systems show that Allspark brings 1.2x-24.0x inference speedup for various visual Transformers over baselines. Compared to Nvidia V100 GPU, Allspark-enriched PIM system yields average speedups of 2.3x and energy savings of 20x-55x., Comment: accepted by IEEE Transactions on Computers

Quantum operations by utilizing the underlying geometric phases produced in physical systems are favoured due to its potential robustness. When a system in a non-degenerate eigenstate undergoes an adiabatically cyclic evolution dominated by its Hamiltonian, it will get a geometric phase, referred to as the Berry Phase. While a non-adiabatically cyclic evolution produces an Aharonov-Anandan geometric phase. The two types of Abelian geometric phases are extended to the non-Abelian cases, where the phase factors become matrix-valued and the transformations associated with different loops are non-commutable. Abelian and non-Abelian (holonomic) operations are prevalent in discrete variable systems, whose limited (say, two) energy levels, form the qubit. While their developments in continuous systems have also been investigated, mainly due to that, bosonic modes (in, such as, cat states) with large Hilbert spaces, provide potential advantages in fault-tolerant quantum computation. Here we propose a feasible scheme to realize non-adiabatic holonomic quantum logic operations in continuous variable systems with cat codes. We construct arbitrary single-qubit (two-qubit) gates with the combination of single- and two-photon drivings applied to a Kerr Parametric Oscillator (KPO) (the coupled KPOs). Our scheme relaxes the requirements of the previously proposed quantum geometric operation strategies in continuous variable systems, providing an effective way for quantum control.

In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circuit design cycles. To achieve the desired performance and specifications, various geometrical symmetry constraints must be carefully considered during the analog layout process. However, the manual labeling of these constraints by experienced analog engineers is a laborious and time-consuming process. To handle the costly runtime issue, we propose a graph-based learning framework to automatically extract symmetric constraints in analog circuit layout. The proposed framework leverages the connection characteristics of circuits and the devices' information to learn the general rules of symmetric constraints, which effectively facilitates the extraction of device-level constraints on circuit netlists. The experimental results demonstrate that compared to state-of-the-art symmetric constraint detection approaches, our framework achieves higher accuracy and F1-score., Comment: 11 pages,10 figures, 6 tables, 1 algorithm

Sparse matrix multiplication (SpMM) is widely applied to numerous domains, such as graph processing, machine learning, and data analytics. However, inner product based SpMM induces redundant zero-element computing for mismatched nonzero operands, while outer product based approach lacks input reuse across Process Elements (PEs) and poor output locality for accumulating partial sum (psum) matrices. Besides, current works only focus on sparse-sparse matrix multiplication (SSMM) or sparse-dense matrix multiplication (SDMM), rarely performing efficiently for both. To address these problems, this paper proposes an unified SpMM accelerator, called IOPS, hybridizing inner with outer products. It reuses the input matrix among PEs with inner product dataflow, and removes zero-element calculations with outer product approach in each PE, which can efficiently process SSMM and SDMM. Moreover, an address mapping method is designed to accumulate the irregular sparse psum matrices, reducing the latency and DRAM access of psum accumulating. Furthermore, an adaptive partition strategy is proposed to tile the input matrices based on their sparsity ratios, effectively utilizing the storage of architecture and reducing DRAM access. Compared with the SSMM accelerator, SpArch, we achieve 1.7x~6.3x energy efficiency and 1.2x~4.4x resource efficiency, with 1.4x~2.1x DRAM access saving.

Analog in-memory computing (AiMC) is an emerging technology that shows fantastic performance superiority for neural network acceleration. However, as the computational bit-width and scale increase, high-precision data conversion and long-distance data routing will result in unacceptable energy and latency overheads in the AiMC system. In this work, we focus on the potential of in-charge computing and in-time interconnection and show an innovative AiMC architecture, named AiDAC, with three key contributions: (1) AiDAC enhances multibit computing efficiency and reduces data conversion times by grouping capacitors technology; (2) AiDAC first adopts row drivers and column time accumulators to achieve large-scale AiMC arrays integration while minimizing the energy cost of data movements. (3) AiDAC is the first work to support large-scale all-analog multibit vector-matrix multiplication (VMM) operations. The evaluation shows that AiDAC maintains high-precision calculation (less than 0.79% total computing error) while also possessing excellent performance features, such as high parallelism (up to 26.2TOPS), low latency (<20ns/VMM), and high energy efficiency (123.8TOPS/W), for 8bits VMM with 1024 input channels., Comment: 6 pages, 8 figures

This paper proposes an application mapping algorithm, BandMap, for coarse-grained reconfigurable array (CGRA), which allocates the bandwidth in PE array according to the transferring demands of data, especially the data with high spatial reuse, to reduce the routing PEs. To cover bandwidth allocation, BandMap maps the data flow graphs (DFGs), abstracted from applications, by solving the maximum independent set (MIS) on a mixture of tuple and quadruple resource occupation conflict graph. Compared to a state-of-art BusMap work, Bandmap can achieve reduced routing PEs with the same or even smaller initiation interval (II).

With the widespread use of deep neural networks(DNNs) in intelligent systems, DNN accelerators with high performance and energy efficiency are greatly demanded. As one of the feasible processing-in-memory(PIM) architectures, 3D-stacked-DRAM-based PIM(DRAM-PIM) architecture enables large-capacity memory and low-cost memory access, which is a promising solution for DNN accelerators with better performance and energy efficiency. However, the low-cost characteristics of stacked DRAM and the distributed manner of memory access and data storing require us to rebalance the hardware design and DNN mapping. In this paper, we propose NicePIM to efficiently explore the design space of hardware architecture and DNN mapping of DRAM-PIM accelerators, which consists of three key components: PIM-Tuner, PIM-Mapper and Data-Scheduler. PIM-Tuner optimizes the hardware configurations leveraging a DNN model for classifying area-compliant architectures and a deep kernel learning model for identifying better hardware parameters. PIM-Mapper explores a variety of DNN mapping configurations, including parallelism between branches of DNN, DNN layer partitioning, DRAM capacity allocation and data layout pattern in DRAM to generate high-hardware-utilization DNN mapping schemes for various hardware configurations. The Data-Scheduler employs an integer-linear-programming-based data scheduling algorithm to alleviate the inter-PIM-node communication overhead of data-sharing brought by DNN layer partitioning. Experimental results demonstrate that NicePIM can optimize hardware configurations for DRAM-PIM systems effectively and can generate high-quality DNN mapping schemes with latency and energy cost reduced by 37% and 28% on average respectively compared to the baseline method., Comment: 13 pages

Bit-serial architectures can handle Neural Networks (NNs) with different weight precisions, achieving higher resource efficiency compared with bit-parallel architectures. Besides, the weights contain abundant zero bits owing to the fault tolerance of NNs, indicating that bit sparsity of NNs can be further exploited for performance improvement. However, the irregular proportion of zero bits in each weight causes imbalanced workloads in the Processing Element (PE) array, which degrades performance or induces overhead for sparse processing. Thus, this paper proposed a bit-sparsity quantization method to maintain the bit sparsity ratio of each weight to no more than a certain value for balancing workloads, with little accuracy loss. Then, we co-designed a sparse bit-serial architecture, called Bit-balance, to improve overall performance, supporting weight-bit sparsity and adaptive bitwidth computation. The whole design was implemented with 65nm technology at 1 GHz and performs at 326-, 30-, 56-, and 218-frame/s for AlexNet, VGG-16, ResNet-50, and GoogleNet respectively. Compared with sparse bit-serial accelerator, Bitlet, Bit-balance achieves 1.8x~2.7x energy efficiency (frame/J) and 2.1x~3.7x resource efficiency (frame/mm2)., Comment: 10 pages 17 figures

Modern field programmable gate array(FPGA) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. And FPGA-based partially dynamically reconfigurable system(FPGA-PDRS) can be used to accelerate computing and improve computing flexibility. However, the traditional design of FPGA-PDRS is based on manual design. Implementing the automation of FPGA-PDRS needs to solve the problems of task modules partitioning, scheduling, and floorplanning on heterogeneous resources. Existing works only partly solve problems for the automation process of FPGA-PDRS or model homogeneous resource for FPGA-PDRS. To better solve the problems in the automation process of FPGA-PDRS and narrow the gap between algorithm and application, in this paper, we propose a complete workflow including three parts, pre-processing to generate the list of task modules candidate shapes according to the resources requirements, exploration process to search the solution of task modules partitioning, scheduling, and floorplanning, and post-optimization to improve the success rate of floorplan. Experimental results show that, compared with state-of-the-art work, the proposed complete workflow can improve performance by 18.7\%, reduce communication cost by 8.6\%, on average, with improving the resources reuse rate of the heterogeneous resources on the chip. And based on the solution generated by the exploration process, the post-optimization can improve the success rate of the floorplan by 14\%.

Sparsity is an intrinsic property of convolutional neural network(CNN) and worth exploiting for CNN accelerators, but extra processing comes with hardware overhead, causing many architectures suffering from only minor profit. Meanwhile, systolic array has been increasingly competitive on CNNs acceleration for its high spatiotemporal locality and low hardware overhead. However, the irregularity of sparsity induces imbalanced workload under the rigid systolic dataflow, causing performance degradation. Thus, this paper proposed a systolicarray-based architecture, called Sense, for sparse CNN acceleration by model-hardware co-design, achieving large performance improvement. To balance input feature map(IFM) and weight loads across Processing Element(PE) array, we applied channel clustering to gather IFMs with approximate sparsity for array computation, and co-designed a load-balancing weight pruning method to keep the sparsity ratio of each kernel at a certain value with little accuracy loss, improving PE utilization and overall performance. Additionally, Adaptive Dataflow Configuration is applied to determine the computing strategy based on the storage ratio of IFMs and weights, lowering 1.17x-1.8x DRAM access compared with Swallow and further reducing system energy consumption. The whole design is implemented on ZynqZCU102 with 200MHz and performs at 471-, 34-, 53- and 191-image/s for AlexNet, VGG-16, ResNet-50 and GoogleNet respectively. Compared against sparse systolic-array-based accelerators, Swallow, FESA and SPOTS, Sense achieves 1x-2.25x, 1.95x-2.5x and 1.17x-2.37x performance improvement on these CNNs respectively with reasonable overhead., Comment: 14 pages, 29 figures, 6 tables, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

We propose a protocol to realize nonadiabatic geometric quantum computation of small-amplitude Schr\"odinger cat qubits via invariant-based reverse engineering. We consider a system with a two-photon driven Kerr nonlinearity, which provides a pair of dressed even and odd coherent states, i.e., Schr\"odinger cat states for fault-tolerant quantum computations. An additional coherent field is applied to linearly drive a cavity mode, to induce oscillations between dressed cat states. By designing this linear drive with invariant-based reverse engineering, nonadiabatic geometric quantum computation with cat qubits can be implemented. The performance of the protocol is estimated by taking into account the influence of systematic errors, additive white Gaussian noise, and decoherence including photon loss and dephasing. Numerical results demonstrate that our protocol is robust against these negative factors. Therefore, this protocol may provide a feasible method for nonadiabatic geometric quantum computation in bosonic systems., Comment: 13 pages, 8 figures, has been published as a Regular Article in Physical Review Research

Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this paper, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. Firstly, we propose a method to generate brain-network-inspired topologies with limited scale-free and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications and the modular topology, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator BookSim2 is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the NoC design generated by the proposed method presents significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs., Comment: 19 pages, 15 figures, 8 tables, accepted by ACM TODAES

In this paper, we propose a scheme for implementing the nonadiabatic holonomic quantum computation (NHQC+) of two Rydberg atoms by using invariant-based reverse engineering (IBRE). The scheme is based on F\"orster resonance induced by strong dipole-dipole interaction between two Rydberg atoms, which provides a selective coupling mechanism to simply the dynamics of system. Moreover, for improving the fidelity of the scheme, the optimal control method is introduced to enhance the gate robustness against systematic errors. Numerical simulations show the scheme is robust against the random noise in control fields, the deviation of dipole-dipole interaction, the F\"orster defect, and the spontaneous emission of atoms. Therefore, the scheme may provide some useful perspectives for the realization of quantum computation with Rydberg atoms.

A protocol is proposed to generate singlet states of three logical qubits constructed by pairs of spins. Single and multiple operations of logical qubits are studied for the construction of an effective Hamiltonian, with which robust control fields are derived with invariant-based reverse engineering and optimal control. Moreover, systematic errors are further compensated by periodic modulation for better robustness. Furthermore, resistance to decoherence of the protocol is also shown with numerical simulations. Therefore, the protocol may provide useful perspectives for generations of logical qubit entanglement in spin systems.

We propose a protocol to realize atomic nonadiabatic holonomic quantum computation (NHQC) with two computational atoms and an auxiliary atom. Dynamics of the system is analyzed in the regime of Rydberg blockade, and robust laser pulses are designed via reverse engineering, so that quantum gates can be easily realized with high fidelities. In addition, we also study the evolution suffering from dissipation with a master equation. The result indicates that decays of atoms can be heralded by measuring the state of the auxiliary atom, and nearly perfect unitary evolution can be obtained if the auxiliary atom remains in its Rydberg state. Therefore, the protocol may be helpful to realize NHQC in dissipative environment.

We present a scheme to realize precise discrimination of chiral molecules in a cavity. Assisted by additional laser pulses, cavity fields can evolve to different coherence states with contrary-sign displacements according to the handedness of molecules. Consequently, the handedness of molecules can be read out with homodyne measurement on the cavity, and the successful probability is nearly unity without very strong cavity fields. Numerical results show that the scheme is insensitive to errors, noise and decoherence. Therefore, the scheme may provide helpful perspectives for accurate discrimination of chiral molecules.

Nonadiabatic holonomic quantum computation has attracted increasing interest because of its robustness. In this paper, based on the shortcuts to adiabaticity (STA), we propose a scheme to construct a three-qubit nonadiabatic holonomic gate in a cavity quantum electrodynamics system. In the scheme, the three-qubit holonomic gate is implemented in a single step. Besides, numerical simulations show that the constructed holonomic quantum gate holds the characteristics of high-fidelity, decoherence-resistance and error-immunity., Comment: 13 pages, 8 figures

Based on shortcuts to adiabaticity and quantum Zeno dynamics, we present a protocol to implement quantum state transfer (QST) in a quantum spin-1/2 chain. In the protocol, the complex Hamiltonian of an $N$-site system is simplified, and a simple effective Hamiltonian is present. It is shown that only the control of the coupling strengths between the boundary spins and the bulk spins are required for QST. Numerical simulations demonstrate that the protocol possesses high efficiency and is robust against the decay and the fluctuations of the control fields. The protocol might provide an alternative choice for transferring quantum states via spin chain systems., Comment: 9 pages, 6 figures, has been accepted by Phys. Rev. A

We introduce a simple yet versatile protocol to inverse engineer the time-dependent Hamiltonian in two- and three level systems. In the protocol, by utilizing a universal SU(2) transformation, a given speedup goal can be obtained with large freedom to select the control parameters. As an illustration example, the protocol is applied to perform population transfer between nitrogen-vacancy (NV) centers in diamond. Numerical simulation shows that the speed of the present protocol is fast compared with that of the adiabatic process. Moreover, the protocol is also tolerant to decoherence and experimental parameter fluctuations. Therefore, the protocol may be useful for designing an experimental feasible Hamiltonian to engineer a quantum system., Comment: 11 pages, 8 figures, has been accepted by Physical Review A

In this paper, we propose a protocol for complete Bell-state analysis for two superconducting-quantum-interference-device qubits. The Bell-state analysis could be completed by using a sequence of microwave pulses designed by the transition- less tracking algorithm, which is an useful method in the technique of shortcut to adiabaticity. After the whole process, the information for distinguishing four Bell states will be encoded on two auxiliary qubits, while the Bell states keep unchanged. One can read out the information by detecting the auxiliary qubits. Thus the Bell-state analysis is nondestructive. The numerical simulations show that the protocol possesses high success probability of distinguishing each Bell state with current experimental technology even when decoherence is taken into account. Thus, the protocol may have potential applications for the information readout in quantum communications and quantum computations in superconducting quantum networks., Comment: 22 pages, 5 figures, has been accepted by Physical Review A

In this paper, a scheme is put forward to design pulses which drive a three-level system based on the reverse engineering with Lewis-Riesenfeld invariant theory. The scheme can be applied to a three-level system even when the rotating-wave approximation (RWA) can not be used. The amplitudes of pulses and the maximal values of detunings in the system could be easily controlled by adjusting control parameters. We analyze the dynamics of the system by an invariant operator, so additional couplings are unnecessary. Moreover, the approaches to avoid singularity of pulses are studied and several useful results are obtained. We hope the scheme could contribute to fast quantum information processing without RWA., Comment: 9 pages 9 figures, has been accepted for publication as a Regular Article in Annalen der Physik

In this paper, we investigate the quantum transfer for the system with three-level $\Lambda$-type structure, and construct a shortcut to the adiabatic passage via picture transformation to speed up the evolution. We can design the pulses directly without any additional couplings. Moreover, by choosing suitable control parameters, the Rabi frequencies of pulses can be expressed by the linear superpositions of Gaussian functions, which could be easily realized in experiments. Compared with the previous works using the stimulated Raman adiabatic passage, the quantum transfer can be significantly accelerated with the present scheme., Comment: 16 pages, 5 figures, has been accepted by Annals of Physics

In this paper, we propose a protocol to prepare W states with superconducting quantum interference devices (SQUID) by using dressed states. Through choosing a set of dressed states suitably, the protocol can be used to accelerate the adiabatic passages while additional couplings are unnecessary. Moreover, we can optimize the evolution of the system with the restraint to the populations of the intermediate states by choosing suitable controlled parameters. Numerical simulations show that the protocol is robust against the parameter variations and decoherence mechanisms. Furthermore, the protocol is faster and more robust against the dephasing, compared with that by the adiabatic passages. As for the Rabi frequencies of pulses designed by the method, they can be expressed by the linear superpositions of Gaussian functions, which does not increase difficulties to the experiments. In addition, the protocol could be controlled and manipulated easily in experiments with a circuit quantum electrodynamics system., Comment: 14 pages (one column), 8 figures, has been accepted by Physical Review A

We propose an effective and flexible scheme for reverse engineering of a Hamiltonian by designing the evolution operators to eliminate the terms of Hamiltonian which are hard to be realized in practice. Different from transitionless quantum driving (TQD) [31], the present scheme is focus on only one or parts of moving states in a D-dimension (D > 3) system. The numerical simulation shows that the present scheme not only contains the results of TQD, but also has more free parameters, which make this scheme more flexible. An example is given by using this scheme to realize the population transfer for a Rydberg atom. The influences of various decoherence processes are discussed by numerical simulation and the result shows that the scheme is fast and robust against the decoherence and operational imperfection. Therefore, this scheme may be used to construct a Hamiltonian which can be realized in experiments, Comment: One column, 13 pages, 6 figures, has been accepted by Scientific Reports

In this paper, we construct a faithful representation with the lowest dimension for every complex Lie algebra in dimension $\leq 4$. In particular, in our construction, in the case that the faithful representation has the same dimension of the Lie algebra, it can induce an \'etale affine representation with base zero which has a natural and simple form and gives a compatible left-symmetric algebra on the Lie algebra. Such affine representations do not contain any nontrivial one-parameter subgroups of translation., Comment: 11 pages, 4 tables, appear in Communications in Algebra

This paper reviews the literature on early child development among Koreans, with a focus on autism spectrum disorders (ASD). The literature review of 951 abstracts in English, 101 abstracts in Korean and 27 full articles published from 1994 to 2011 was performed to understand the presentation of and response to ASD in Korean culture. Based on research to date on the identification, description, and treatment of ASD in Korean populations, we argue that at both conceptual and practical levels, early child development and interventions must be understood within cultural context. Culturally informed research on ASD is vital for increasing awareness of the importance of early intervention and the need for educational and psychological services in countries in which autism is stigmatized, misdiagnosed or undiagnosed.