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Graph Neural Networks (GNNs) are becoming increasingly popular for graph-based learning tasks such as point cloud processing due to their state-of-the-art (SOTA) performance. Nevertheless, the research community has primarily focused on improving model expressiveness, lacking consideration of how to design efficient GNN models for edge scenarios with real-time requirements and limited resources. Examining existing GNN models reveals varied execution across platforms and frequent Out-Of-Memory (OOM) problems, highlighting the need for hardware-aware GNN design. To address this challenge, this work proposes a novel hardware-aware graph neural architecture search framework tailored for resource constraint edge devices, namely HGNAS. To achieve hardware awareness, HGNAS integrates an efficient GNN hardware performance predictor that evaluates the latency and peak memory usage of GNNs in milliseconds. Meanwhile, we study GNN memory usage during inference and offer a peak memory estimation method, enhancing the robustness of architecture evaluations when combined with predictor outcomes. Furthermore, HGNAS constructs a fine-grained design space to enable the exploration of extreme performance architectures by decoupling the GNN paradigm. In addition, the multi-stage hierarchical search strategy is leveraged to facilitate the navigation of huge candidates, which can reduce the single search time to a few GPU hours. To the best of our knowledge, HGNAS is the first automated GNN design framework for edge devices, and also the first work to achieve hardware awareness of GNNs across different platforms. Extensive experiments across various applications and edge devices have proven the superiority of HGNAS. It can achieve up to a 10.6x speedup and an 82.5% peak memory reduction with negligible accuracy loss compared to DGCNN on ModelNet40., Comment: Accepted by IEEE Transactions on Computers

Deep neural networks have delivered remarkable performance and have been widely used in various visual tasks. However, their huge size causes significant inconvenience for transmission and storage. Many previous studies have explored model size compression. However, these studies often approach various lossy and lossless compression methods in isolation, leading to challenges in achieving high compression ratios efficiently. This work proposes a post-training model size compression method that combines lossy and lossless compression in a unified way. We first propose a unified parametric weight transformation, which ensures different lossy compression methods can be performed jointly in a post-training manner. Then, a dedicated differentiable counter is introduced to guide the optimization of lossy compression to arrive at a more suitable point for later lossless compression. Additionally, our method can easily control a desired global compression ratio and allocate adaptive ratios for different layers. Finally, our method can achieve a stable $10\times$ compression ratio without sacrificing accuracy and a $20\times$ compression ratio with minor accuracy loss in a short time. Our code is available at https://github.com/ModelTC/L2_Compression .

Graph neural networks (GNNs) have emerged as a popular strategy for handling non-Euclidean data due to their state-of-the-art performance. However, most of the current GNN model designs mainly focus on task accuracy, lacking in considering hardware resources limitation and real-time requirements of edge application scenarios. Comprehensive profiling of typical GNN models indicates that their execution characteristics are significantly affected across different computing platforms, which demands hardware awareness for efficient GNN designs. In this work, HGNAS is proposed as the first Hardware-aware Graph Neural Architecture Search framework targeting resource constraint edge devices. By decoupling the GNN paradigm, HGNAS constructs a fine-grained design space and leverages an efficient multi-stage search strategy to explore optimal architectures within a few GPU hours. Moreover, HGNAS achieves hardware awareness during the GNN architecture design by leveraging a hardware performance predictor, which could balance the GNN model accuracy and efficiency corresponding to the characteristics of targeted devices. Experimental results show that HGNAS can achieve about $10.6\times$ speedup and $88.2\%$ peak memory reduction with a negligible accuracy loss compared to DGCNN on various edge devices, including Nvidia RTX3080, Jetson TX2, Intel i7-8700K and Raspberry Pi 3B+., Comment: Accepted by DAC'23

The electronic and optoelectronic properties of two dimensional materials have been extensively explored in graphene and layered transition metal dichalcogenides (TMDs). Spintronics in these two-dimensional materials could provide novel opportunities for future electronics, for example, efficient generation of spin current, which should enable the efficient manipulation of magnetic elements. So far, the quantitative determination of charge current induced spin current and spin-orbit torques (SOTs) on the magnetic layer adjacent to two-dimensional materials is still lacking. Here, we report a large SOT generated by current-induced spin accumulation through the Rashba-Edelstein effect in the composites of monolayer TMD (MoS$_2$ or WSe$_2$)/CoFeB bilayer. The effective spin conductivity corresponding to the SOT turns out to be almost temperature-independent. Our results suggest that the charge-spin conversion in the chemical vapor deposition-grown large-scale monolayer TMDs could potentially lead to high energy efficiency for magnetization reversal and convenient device integration for future spintronics based on two-dimensional materials., Comment: accepted version

A new phototransistor based on the mechanically-exfoliated single-layer MoS2 nanosheet is fabricated and its light-induced electric properties are investigated in details. Photocurrent generated from the phototransistor is solely determined by the illuminated optical power at a constant drain or gate voltage. The switching behavior of photocurrent generation and annihilation can be completely finished within ca. 50 ms and it shows good stability. Especially, the single-layer MoS2 phototransistor exhibits a better photoresponsivity as compared with the graphene-based device. The unique characteristics of incident-light control, prompt photoswitching and good photoresponsivity from the MoS2 phototransistor pave an avenue to develop the single-layer semiconducting materials for multi-functional optoelectronic device applications in future., Comment: 28 pages

Two-dimensional (2D) materials, such as molybdenum disulfide (MoS2), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS2 allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene's advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors and photodetectors made from few-layer MoS2 show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multi-stage circuits and logic building blocks on MoS2 to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between two to twelve transistors seamlessly integrated side-by-side on a single sheet of bilayer MoS2. Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions., Comment: 23 pages, 5 figures, Supplementary Information, Accepted for publication in Nano Letters

The two-dimensional layer of molybdenum disulfide (MoS2) has recently attracted much interest due to its direct-gap property and potential applications in optoelectronics and energy harvesting. However, the synthetic approach to obtain high quality and large-area MoS2 atomic thin layers is still rare. Here we report that the high temperature annealing of a thermally decomposed ammonium thiomolybdate layer in the presence of sulfur can produce large-area MoS2 thin layers with superior electrical performance on insulating substrates. Spectroscopic and microscopic results reveal that the synthesized MoS2 sheets are highly crystalline. The electron mobility of the bottom-gate transistor devices made of the synthesized MoS2 layer is comparable with those of the micromechanically exfoliated thin sheets from MoS2 crystals. This synthetic approach is simple, scalable and applicable to other transition metal dichalcogenides. Meanwhile, the obtained MoS2 films are transferable to arbitrary substrates, providing great opportunities to make layered composites by stacking various atomically thin layers., Comment: manuscript submitted on 11-Dec-2011, revision submitted on 16-Feb-2012