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1. Design Principles for Packet Deparsers on FPGAs

2. Bridging the Gap: FPGAs as Programmable Switches

3. Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design

4. One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing

5. P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs

6. Extern Objects in P4: an ROHC Header Compression Scheme Case Study

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