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Railway infrastructures are characterized by useful lives of more than 30 years. Such long useful lives make long-term maintenance strategies crucial. In this paper a simulation ap-proach for the whole useful life of ballasted tracks is presented. It relies on a stochastic model of the ageing and restoration process of railway track geometry and a heuristic algorithm for maintenance interventions planning. Its objective is the simu-lation, analysis and optimization of track geometry maintenance strategies during the whole service life of the track, under con-sideration of the ageing and restoration characteristics of each track sector and the resources available for maintenance. The results of a simulation are a list of all tamping interventions during the useful life of the track and the course of the track geometry deviation at each track sector during the simulated time. On the basis of this data, fundamental features of the track geometry quality during the whole track useful life can be assessed. After a description of the simulation procedure and the enumeration of the input and output data, the approach is validated by means of a case study basing on real data of a French TGV line. In the case study, the long-term effects of an adaptive intervention threshold are investigated. With this aim, two strategies are simulated, one with a constant and one with an adaptive intervention threshold. The advantages and drawbacks of each strategy are then analysed and compared. [ABSTRACT FROM AUTHOR]

This paper deals with the process of optimizing embedded digital signal processor (DSP) systems. Although efficiency goals differ in every system, optimization normally focuses on program execution speed, memory usage, and power consumption. DSP are a specialized type of microprocessor that handles certain types of algorithms extremely efficient for real-time signal processing. Compilers perform optimization techniques that are both machine dependent and independent. A particularly important generic optimization technique is loop unrolling. The trade-off in loop unrolling is that it requires more instruction code, and more registers and cache space for data. Because DSP are number crunchers by nature, their assembly instruction sets may include some instructions for mathematical operations used often in algorithms. Assembly operations require different lengths of time due to memory-access delays and differences in parallel function units. When the compiler predicts these conditions, it can force the processor to wait by inserting no operation cycles into the instruction stream. Software pipelining inherently improves execution speed, but it may not be possible if unnecessary dependencies exist. Direct memory access control is essential to the operation of high-performance DSP, allowing data transfers to proceed with little or no intervention from the processor core.

Presents highlights of the 2000 Computer Conference & Showcase of the National Petrochemical & Refiners Association. Papers presented; Discussion on difficulties with online optimization in actual plant operation and equipment performance; Trends in packaged systems utilizing dynamic models.

Presents the National Petroleum Refiners Association's annual Computer Conference and Showcase held on November 16 -19, 1997 which includes papers and breakout sessions on process control, information systems and planning and scheduling. Exploration of the topic on closed-loop, real-time optimization (CLRTO); Background of CLRTO; Problems with CLRTO; Importance of proper feed characterization to CLRTO.