Search

This article describes a fully integrated 3.2 GHz synthesizer with a self-biasing current source for a 5 GHz wireless LAN receiver in the lower UNII hand from 5.15 to 5.35 GHz. The circuit has been designed using a 0.18 μm one-poly six-metal CMOS technology of UMC. OFDM is considered one of the most attractive transmission techniques for future wireless multimedia communications in frequency selective channels. However, it also has the disadvantage of an increased sensitivity to phase noise generated by the local oscillators inside a communication transceiver In order to achieve a high performance device, therefore, the simulation tool Simusyn has been, implemented to predict the phase noise, spurious emissions and lock time of the synthesizer before its fabrication. The synthesizer consumes 53 mW with a power supply of 3.3 V Furthermore, it has a bandwidth of 20 kHz and a phase noise of -118 dBc/Hz at 1 MHz offset frequency resulting in a total integrated phase noise over the channel bandwidth less than -32 dBc. Finally, the spurious sidebands at the center of adjacent channels do not exceed -64 dBc. These results made the circuit suitable inside a UNII band 5 GHz wireless LAN receiver. [ABSTRACT FROM AUTHOR]