76 results on '"Vlsi architecture"'
Search Results
2. Hardware Architecture for List GRAND (LGRAND)
3. Hardware Architecture for GRAND with ABandonment (GRANDAB)
4. Hardware Architecture for Ordered Reliability Bits GRAND (ORBGRAND)
5. Triple Linear Congruential Generator-Based Hardware-Efficient Pseudorandom Bit Generation
6. Design and Implementation of an Efficient VLSI Architecture for 10T Full Adder Used in Ultra Low Power Applications
7. An Integrated VLSI Architecture for Forward and Backward Lifting Scheme Discrete Wavelet Transform Using FinFET Device
8. High Level Synthesis of VLSI Based Image Scaling Architecture for High Definition Displays
9. A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations
10. An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding
11. High Frame Rate Real-Time Scene Change Detection System
12. A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra Prediction in HEVC
13. VLSI Architecture for Fast Three Step Search Algorithm
14. An Efficient Zigzag Scanning and Entropy Coding Architecture Design
15. Signal Processing for High-Speed Links
16. Architecture of Image Encryption Hardware Using Two Dimensional Cellular Automata
17. VLSI Architecture for Real-Time Cloud Detection in Optical Remote Sensing Image
18. Forward Plans
19. Conclusions
20. Efficient K-Means VLSI Architecture for Vector Quantization
21. Memory Efficient VLSI Architecture for QCIF to VGA Resolution Conversion
22. Fractional Full-Search Motion Estimation VLSI Architecture for H.264/AVC
23. A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder
24. A High-Speed Parallel Architecture for Stereo Matching
25. Improvement of Image Transform Calculation Based on a Weighted Primitive
26. A Cellular Automaton Crowd Tracking System for Modelling Evacuation Processes
27. A Cellular Automata Simulation Tool for Modelling and Automatic VLSI Implementation of the Oxidation Process in Integrated Circuit Fabrication
28. A New VLSI Architecture of Lifting-Based DWT
29. Efficient Linear Array for Multiplication over NIST Recommended Binary Fields
30. Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform
31. An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile
32. Faster DTMF Decoding
33. Media Informatics at the Technical University of Dresden
34. A Novel Symbol Estimation Algorithm for LTE Standard
35. Dedicated VLSI Architectures for Adaptive Interference Suppression in Wireless Communication Systems
36. Parallel and Distributed Solutions for the Optimal Binary Search Tree Problem
37. Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors
38. Embedded Software for Video
39. Cryptographic Reuse Library
40. Low-Power Custom Regular Processor Synthesis Flow
41. Scalable hardware-algorithms for binary prefix sums
42. Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis
43. Highly Regular Architectures for Finite Field Computation Using Redundant Basis
44. VLSI Implementation: Search Engine I (2D Array)
45. VLSI Implementation: Search Engine II (1D Array)
46. Design Space Motion Estimation Architectures
47. Introduction
48. Neuromorphic Learning VLSI Systems: A Survey
49. Unfolded Redundant CORDIC VLSI Architectures With Reduced Area and Power Consumption
50. VLSI Architectures for the XYZ Video Codec
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.