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5. Triple Linear Congruential Generator-Based Hardware-Efficient Pseudorandom Bit Generation

6. Design and Implementation of an Efficient VLSI Architecture for 10T Full Adder Used in Ultra Low Power Applications

7. An Integrated VLSI Architecture for Forward and Backward Lifting Scheme Discrete Wavelet Transform Using FinFET Device

9. A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations

10. An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding

11. High Frame Rate Real-Time Scene Change Detection System

12. A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra Prediction in HEVC

14. An Efficient Zigzag Scanning and Entropy Coding Architecture Design

18. Forward Plans

19. Conclusions

20. Efficient K-Means VLSI Architecture for Vector Quantization

21. Memory Efficient VLSI Architecture for QCIF to VGA Resolution Conversion

22. Fractional Full-Search Motion Estimation VLSI Architecture for H.264/AVC

23. A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder

24. A High-Speed Parallel Architecture for Stereo Matching

25. Improvement of Image Transform Calculation Based on a Weighted Primitive

26. A Cellular Automaton Crowd Tracking System for Modelling Evacuation Processes

27. A Cellular Automata Simulation Tool for Modelling and Automatic VLSI Implementation of the Oxidation Process in Integrated Circuit Fabrication

28. A New VLSI Architecture of Lifting-Based DWT

29. Efficient Linear Array for Multiplication over NIST Recommended Binary Fields

30. Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform

31. An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile

32. Faster DTMF Decoding

34. A Novel Symbol Estimation Algorithm for LTE Standard

38. Embedded Software for Video

41. Scalable hardware-algorithms for binary prefix sums

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