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1. Embedding CCSL into Dynamic Logic: A Logical Approach for the Verification of CCSL Specifications

2. PSTeC: A Location-Time Driven Modelling Formalism for Probabilistic Real-Time Systems

3. A Framework for Data-Driven Automata Design

4. Bandwidth Constrained Coordinated HW/SW Prefetching for Multicores

5. Multilayer Cache Partitioning for Multiprogram Workloads

6. Automated Tracing of I/O Stack

7. Scalable Parallelization Strategies to Accelerate NuFFT Data Translation on Multicores

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