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The formation of a SEI layer and its growth cause internal resistance increase and capacity loss, leading to performance degradation of lithium-ion batteries. In order to comprehensively investigate the effects of SEI growth on battery performance, a one-dimensional thermal-electrochemical model was developed. This model is equipped with a growth mechanism of the SEI layer coupled with thermal evolution, based on the diffusional process of the solvent through the SEI layer and the kinetic process at the interface between the solid and liquid phases. The model is able to reveal the effects of diffusivity, reaction kinetics and temperature on SEI layer growth and cell capacity fade. We show that depending on the SEI thickness, the growth can be kinetics-limited or diffusion-limited. With the layer becoming thicker, its growth rate slows down gradually due to increased diffusion resistance. The SEI layer grows faster during charge than discharge due to the difference in the electron flux through the SEI layer and the temperature change during cycling. Temperature rise due to reaction and joule heating accelerates the SEI layer growth, leading to more capacity loss. Our model can provide insights on position-dependent SEI growth rate and be used to guide the strategic monitoring location. [ABSTRACT FROM AUTHOR]

In solar cell technology, surface texturing is essential for reducing the reflectance of cell surfaces and increasing their efficiency. This study employs photo-assisted electrochemical etching (PAECE) to fabricate a hybrid structure comprising a reversed pyramid structure and a high aspect ratio macro-pore on the silicon wafer surface, to reduce cell surface reflectance. The experimental results show that the etching depth of the fabricated macro-pore array structure was approximately 67.1µm and its diameter was approximately 5µm on the 525-µm-thick sample, such that the aspect ratio of the pore was approximately 13.4:1. The mean reflectance of a blank silicon wafer is 37.4% in the wavelength range of 280-800nm; however, the reversed pyramid created using a 120-min PAECE process and 25-min RIE can reduce the mean reflectance to 0.7% on the 380-µm-thick sample. The novel fabrication process developed in this study is low cost and the hybrid structure can be applied to antireflection structures in single crystalline silicon solar cells. [ABSTRACT FROM AUTHOR]