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Partial shading condition drastically reduces the maximum power output of photovoltaic array. Partial shading occurs due to several factors, such as flying birds, trees, and passing clouds. Many ways can be mitigated partial shading problems in photovoltaic (PV) array. One among the way is reconfiguration techniques, namely reconfigure the location of PV modules in PV array based on irradiance levels in order to distribute shading effects and increasing maximum power. This paper proposed an optimal SuDoKu reconfiguration pattern for $9\times 9$ total-cross-tied (TCT) PV array to improve maximum power under partial shading conditions. In this approach, the physical location of PV modules in TCT array are rearranged based on optimal SuDoKu style without altering the electrical connections, so that the shading effects can distribute over the array. Further, the performance of proposed pattern investigated with existing SuDoKu pattern under different shading conditions by comparing the global maximum power point, mismatch losses, fill-factor, and efficiency using MATLAB-Simulink. Based on the results of this paper, it concluded that the proposed optimal SuDoKu reconfiguration arrangement is reducing the wiring arrangement and increasing the shading distribution over the array as compared to SuDoKu arrangement. [ABSTRACT FROM AUTHOR]

This paper proposes an adaptive model of modular multilevel converter (MMC) for electromagnetic transient (EMT) simulations. The model is applicable to MMCs with arbitrary numbers of half-bridge and full-bridge submodules. The proposed design includes average value model, arm equivalent model, and detailed equivalent model. It allows smoothly transitioning from one model to another during time-domain simulations depending on the desired accuracy and execution time constraints. Modifications required in conventional MMC models to achieve smooth transitions are presented in the paper. Time-domain initialization methods are developed for each constituting model, including initialization of the appropriate control system blocks. Validity and effectiveness of the proposed adaptive model is demonstrated using EMT simulations of 401-level MMC-HVDC system. [ABSTRACT FROM AUTHOR]

An electrical transient model (ETM) of insulated-gate bipolar transistor (IGBT)-diode switching cell is developed by coupling a temperature-dependent IGBT model with power loss model. The nonlinear behavior of IGBT and the reverse recovery characteristic of the diode are considered in this model to simulate the transient switching waveforms. Based on the transient waveforms of ETM under various operating conditions, the power loss estimation method (PLEM) for IGBT is developed. In addition to traditional modeling techniques that only uses ideal switch, this paper uses the model to replicate the power loss behaviors of semiconductor devices in circuit simulation by looking up tables. The proposed ETM is simulated in PSCAD/EMTDC with nanosecond time step, whereas the overall system application can be simulated with conventional time step in range of microsecond. By this way, the model can promise reasonable accuracy as well as an acceptable fast solving speed. The proposed ETM and PLEM have been implemented in PSCAD/EMTDC simulator and validated by experimental results using a double pulse test bench and boost converter test platform. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel Verilog-A based memristor model for effective simulation and application. Our proposed model captures desired nonlinear characteristics using voltage-based state control. This model is flexible and accurate, it can exhibit all the behaviors of HP memristive device and a general class memristive device resistive random access memory which is important in logic and memory design. Furthermore, we can antiserially connect two proposed models to capture the ideal I – V characteristics of complementary resistive switch (CRS). We demonstrate that our proposed CRS model-based crossbar arrays can significantly reduce sneak path currents with high noise margin compared to traditional memristor-based architectures. [ABSTRACT FROM AUTHOR]

The use of formal models to describe early versions of the structure and the behavior of a system has become common practice in industry. UML and OCL are the de-facto specification languages for these tasks. They allow for capturing system properties and module behavior in an abstract but still formal fashion. At the same time, this enables designers to detect errors or inconsistencies in the initial phases of the design flow—even if the implementation has not already started. Corresponding tools for verification of formal models got established in the recent past. However, verification results are usually not reused in later design steps anymore. In fact, similar verification tasks are applied again, e.g., after the implementation has been completed. This is a waste of computational and human effort. In this paper, we address this problem by proposing a method which checks a given implementation of a system against its corresponding formal method. This allows for transferring verification results already obtained from the formal model to the implementation and, eventually, motivates a new design flow which addresses verification across abstraction levels. This paper describes the applied techniques as well as their orchestration. Afterwards, the applicability of the proposed methodology is demonstrated by means of examples as well as a case study from an industrial context. [ABSTRACT FROM AUTHOR]

We present a physics-based compact model that captures the behavior of phase-transition materials. The model includes a self-heating module that captures the change in temperature with device operation and the resulting phase change. This is the first compact model that captures the temperature-dependent multidomain switching and the hysteresis behavior seen in such devices. The model is implemented in Verilog-A and validated with experimental data for various geometries and temperatures. It is further coupled with industry standard BSIM-BULK, ASM-HEMT, and BSIM-CMG models for SPICE simulation and validated for various phase-transition FETs, illustrating the previously proposed steep switching effect and a subthreshold slope below the Boltzmann limit of 60 mV/decade. [ABSTRACT FROM AUTHOR]

Resistive switching devices are nonlinear electrical components that have drawn great attention in the design of new technologies including memory devices and neuromorphic circuits. In this paper, an SPICE implementation of a novel compact model is presented and put under test by means of different circuit configurations. The model is based on two identical opposite-biased diodes in series with a resistor where the switching behavior is governed by the creation and rupture of multiple conductive channels. Results show that the model is stable under different input sources and amplitudes and, with special interest, in multielement circuits. The model is validated with experimental data available in the literature. Both the corresponding SPICE code and schematic are provided in order to facilitate the model use and assessment. [ABSTRACT FROM PUBLISHER]

The realm of hardware-in-the-loop simulation resorts to field-programmable gate arrays to achieve time steps below 1 \mu\s . Such low time steps are of importance for the aerospace and automotive industries, where power converters have their switching frequencies in the 10- to 200-kHz range. This paper proposes a network tearing technique that allows subsets of switches to be treated independently, alleviates embedded memory requirements, and reduces the computational burden. An iterative algorithm is used to determine the state of naturally commutated switches, thus offering a realistic model of the power converter, independently of its operation mode or topology. A Gauss-Jordan processing unit is implemented to solve interface voltages/currents from the torn circuit. Custom floating-point operators are used to ensure good accuracy, high-frequency operation, and low computational latency. A neutral-point-clamped converter case study is presented to demonstrate the effectiveness of the method. Simulation results are validated against a reference model at a 750-ns time step and a 30-kHz sine pulsewidth modulation switching frequency. [ABSTRACT FROM PUBLISHER]

Generally, battery-fed capacitive loads are charged to high voltages in series of switching cycles with smaller fragments of energy delivered to the load in every cycle to ensure an efficient charging process. In high voltage low power (HVLP) flyback charging circuit, significant portion of input energy drawn from the source in a cycle is utilized by the effective parasitic capacitance of the HV transformer and semiconductor devices and circulated back to the source at the end of the cycle. This reduces the energy delivered to the load per cycle and hence the net energy delivered in the charging process. In this paper, an energy-based analysis and simplified energy-based model for HVLP charging circuits is derived. An energy-based approach is appropriate to describe and define the HVLP converter behavior in terms of load energy component and circulating energy component. The derived energy-based model is extended to obtain analytical closed-form expressions governing the essential parameters of the charging circuit. The proposed energy-based model and analytical formulation of essential parameters are experimentally validated on a 0–2.5 kV programmable high voltage charging circuit prototype fed from 12 V input battery source. [ABSTRACT FROM AUTHOR]

This paper introduces a novel modeling approach that allows to obtain fast simulations of pulsewidth-modulated dc–dc switched-mode power supplies (SMPS). The proposed methodology combines the use of precise switched models during transient evolutions and averaged models during steady-state or slowly varying conditions. In that way, the resulting mixed modeling approach enables to obtain the detailed switching behavior of SMPS in the context of long-term simulations. The commutation between models is automatically performed in runtime by an algorithm that detects the transient or slowly varying condition according to the evolution of some model variables. When the precise switched model is used, the mentioned algorithm also adjusts the averaged model parameters so that its results are accurate irrespective of the operating point. This paper also describes the implementation of the methodology in the Modelica language and reports simulation experiments showing that the results are as accurate as those obtained using precise switched models, but several times faster. [ABSTRACT FROM AUTHOR]

Floating interleaved boost converter (FIBC) is a promising topology of the dc/dc converters to interface the fuel cell with dc bus in a hybrid powertrain. For the efficient control development of power converters, the hardware-in-the-loop (HIL) simulation plays an important role. The accuracy of the real-time model determines the credibility of the HIL simulation. In order to take the power losses and thermal stress into account in the control development, the device-level real-time model is becoming popular in recent years, which can effectively produce device transient voltage and current waveforms, switching power dissipations, and thermal behaviors. In this paper, a device-level electro-thermal model of FIBC is proposed and developed using the field programmable gate array based real-time simulation technology. The FIBC network model can effectively be simulated with a 500-ns time step while producing the insulated-gate bipolar transistor transient switching waveforms authentically with a 5-ns resolution. The switching power losses can thus be estimated in real time and then used for the computation of the IGBT thermal behavior. Therefore, the device junction temperature can be evaluated in the real-time simulation. The accuracy of the proposed FIBC device-level model is validated by the reference model in the Saber offline simulation tool. At last, an embedded PI controller of FIBC is employed in the real-time experiments to verify the effectiveness of the developed model. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of existing and novel behavioral models targeted at the outphasing power amplifier (PA) architecture. A comprehensive comparison of ten modeling strategies is presented in the results. Novel techniques for outphasing PAs, such as vector switched and dual path time series, are also presented for the first time. Investigation of such techniques was driven by the analysis of outphasing operation at minimum output powers, demonstrating the generation of frequency-dependent amplitude and phase deviations, which can be difficult to characterize. The increased robustness was achieved at the cost of additional complexity; for practical implementation, time series coefficient reduction techniques were also evaluated. The results of all modeling approaches are experimentally validated for the wideband operation of an NXP 19-W GaN digital outphasing amplifier module. Considering computational complexity and accuracy for system-level modeling across all presented options, a subset of existing and new models is identified as best suited for modeling outphasing PAs. [ABSTRACT FROM PUBLISHER]

This paper proposes an optimal design method of modular multilevel converter (MMC) levels to approach the reasonable compromise between accuracy and computational efficiency. The entire procedure is benchmarked by a Thévenin equivalent 451-level MMC model. First, the calculation method of the critical maximum simulation time step is proposed to faithfully represent each voltage level of the staircase waveforms. Second, the previously developed improved analytic hierarchy process is adopted to integrate the relative errors of all the main electrical parameters into one comprehensive relative error at each MMC level. Third, the steady state, ac, and dc transient state relative error results as well as the central-processing unit times of all models are normalized and curve fitted based on the benchmark model. Finally, the optimal MMC level is obtained by the plotted curves and the given subjective weights considering the accuracy and efficiency. And the effectiveness and robustness of the proposed method are validated by various simulation scenarios on PSCAD/EMTDC. [ABSTRACT FROM PUBLISHER]

Current nanometer CMOS circuits show an increasing sensitivity to deviations in first-order parameters and suffer from process variations during manufacturing. To properly assess and support test validation of digital designs, low-level fault simulation approaches are utilized to accurately capture the behavior of CMOS cells under parametric faults and process variations as early as possible throughout the design phase. However, low-level simulation approaches exhibit a high computational complexity, especially when variation has to be taken into account. In this paper, a high-throughput parallel fault simulation at switch level is presented. First-order electrical parameters are utilized to capture CMOS-specific functional and timing behavior of complex cells allowing to model faults with transistor granularity and without the need of logic abstraction. Furthermore, variation modeling in cells and transistor devices enables broad and efficient variation analyses of faults over many circuit instances for the first time. The simulation approach utilizes massive parallelization on graphics processing units by exploiting parallelism from cells, stimuli, faults, and circuit instances. Despite the lower abstraction levels of the approach, it processes designs with millions of gates and outperforms conventional fault simulation at logic level in terms of speed and accuracy. [ABSTRACT FROM AUTHOR]

With the increasing penetration of renewable energies in modern power grids, large amounts of voltage source converters (VSCs) have been installed, resulting in many new transient issues. Electromagnetic transient (EMT) simulation plays an essential role in investigating and solving the issues. However, simulation efficiency plunges when object grids contain multiple VSCs, because each switching event incurs modification or re-decomposition of the network matrix in traditional EMT programs, which is very time-consuming. Thus, this paper proposes a VSC model represented by pulse voltage-current source pairs. Accordingly, a unidirectional loosely-coupled solving algorithm is designed. Synthetically, the authors propose a novel EMT simulation approach adaptive to systems with multiple VSCs. The proposed approach keeps the computational network invariable while sufficiently considers detailed switching events, thereby significantly improving the simulation efficiency of the EMTP program without precision loss. [ABSTRACT FROM AUTHOR]

The emerging voltage source converters (VSCs) such as hybrid cascaded multilevel converters (HCMCs) are promising converter technologies which enable higher converter efficiency, compactness, and DC fault resilience for high voltage direct current (HVDC) transmission. However, the large number of switching events due to the converters’ submodules introduces a heavy computational burden for electromagnetic transient (EMT) simulations. Efficient and accurate EMT-type converter models play a vital role in the control and design of HVDC converters. Several computationally efficient models for the HCMCs are proposed in this paper, including the detailed equivalent model (DEM) and several average value models (AVMs) of varying accuracy. Additionally, a combined model is proposed which allows the users to switch among the DEM and AVMs during dynamic simulations. The proposed models are validated against the DEM for dynamic transients. The simulation results demonstrate good modeling accuracy of the proposed models. The AVMs are also shown to significantly improve simulation efficiency compared to the DEM, which is very desirable especially for HCMCs with a large number of submodules. [ABSTRACT FROM AUTHOR]

The large number of switching elements in the modular multilevel converter (MMC) is a challenging problem when modeling the MMC-HVDC systems for the computation of electromagnetic transients. The modeling complexity increases even further when a multiterminal (MT) MMC-HVDC system is used to integrate offshore wind farms (OWFs) with power-electronics-based wind energy converters, such as doubly fed induction generators (DFIGs). This paper compares modeling accuracy and computational performances for various combinations of MMC and OWF models. Onshore and offshore ac fault simulations are performed for an OWF system composed of DFIG-type wind turbines and connected to a practical ac grid through an MT MMC-HVDC system. The OWF system model includes the detailed representation of the offshore collector grid and the associated overcurrent protection. The offshore MMC controls include an offshore fault current limiter and fast OWF power generation reduction-based fault-ride-through function. [ABSTRACT FROM PUBLISHER]

The device-level real-time simulation of power converters is constrained by the contradiction between the required short simulation time step to describe the transient behaviors and the large computational amount caused by the nonlinearities of switches’ models. In this paper, a novel low-latency device-level power converter modeling approach is proposed for field programmable gate array (FPGA)-based real-time simulation. A piecewise linear insulated-gate bipolar transistor (IGBT)/diode transient model is proposed based on the inductive switching behaviors. The switching transient is modeled into four phases, which are identified by the boundaries between three operating regions of IGBT and between two operating modes of a diode. Moreover, each phase is approximated by a linear continuous behavior in order to reduce the real-time computational amounts. Accompanied by the effective boundary identification, the device-level IGBT/diode model can be efficiently integrated into the real-time simulation with low computational latency. A dc–dc–ac topology model is implemented on the FPGA-based real-time platform, as a case study to verify the effectiveness and practicability of the proposed approach. With the help of circuit partitioning techniques, the device-level converter model can be simulated with a 50-ns time step on FPGA. Moreover, the accuracy of FPGA-based simulation results is validated by the error evaluation with respect to the results from offline simulation tools. [ABSTRACT FROM AUTHOR]

The efficiency of multiterminal dc (MTDC) grid simulation decreases with an expansion of its scale and the inclusion of accurate component models. Thus, the variable time-stepping scheme is proposed in this paper to expedite the electromagnetic transient computation. A number of criteria are proposed to evaluate the time-step and regulate it dynamically during simulation. Meanwhile, as the accuracy of results is heavily reliant on the switch model in the modular multilevel converter, the nonlinear behavioral model with a greater accuracy is proposed in addition to the classic ideal model, and their corresponding variable time-stepping schemes are analyzed. Circuit partitioning is effective in accelerating the MTDC grid simulation via fine-grained separation of nonlinearities. A subsequent large number of identical circuits enabled a massively parallel implementation on the graphics processing unit, which achieved a remarkable speedup over the CPU-based implementation. The inclusion of variable time-stepping schemes eventually makes the simulation of MTDC grid with highly detailed nonlinear switch models feasible. The results are validated by commercial device-level and system-level simulation tools. [ABSTRACT FROM AUTHOR]

Detailed high-order models of the insulated-gate bipolar transistor (IGBT) and the diode are rarely included in power converters for large-scale system-level electromagnetic transient (EMT) simulation on the CPU, due to the nonlinear characteristics albeit they are more accurate. The massively parallel architecture of the graphics processing unit (GPU) enables a lower computational burden by avoiding the computation of complex devices repetitively in a sequential manner and thus is utilized in this paper to simulate the wind farm-integrated multiterminal dc (MTdc) grid based on the modular multilevel converter (MMC). Fine-grained circuit partitioning is proposed so that the nonlinear switching elements are physically separated with the smallest circuit unit. By implementing these subsystems with the same attributes as a GPU program and computing it in a massively parallel manner, it is demonstrated that the GPU is able to achieve a significant speedup over multicore CPUs and its computation time incremental is much smaller when the MMC level scales up. The improved insight and accuracy of the proposed modeling methodology and the designed GPU program are validated at the system- and device-level by off-line commercial simulation tools. [ABSTRACT FROM AUTHOR]

Power converters in the system-level real-time simulation are usually emulated by L/C-based associated discrete circuit (L/C-ADC). However, the L/C-ADC approaches may suffer from two issues: How to mitigate the unacceptable virtual power loss especially in high-frequency applications, and how to tune LC parameters setting which is affected by the external circuit. This paper proposes a novel generalized associated discrete circuit (G-ADC) model with parameterized history current sources. By utilizing the stability region of the feasible parameter space, the optimized G-ADC models with the best damping characteristic are developed for both two-level and three-level converters. The analytical results also guarantee that the parameters of the optimized G-ADC model are independent of the external circuit for most power grid applications. Furthermore, an field programmable gate array (FPGA)-based real-time simulation platform is built to verify the feasibility of the proposed scheme. Extensive simulation and hardware-in-loop experiment results demonstrate the effectiveness and superiority of best-damped models as well as the modeling flexibility corresponding to insensitivity to operating conditions and external system parameters. [ABSTRACT FROM AUTHOR]

This paper proposes a novel FPGA-based matrix-inversion technique that is specifically tailored and optimized for real-time electromagnetic transients simulation of power electronic converters with high switching frequency. This is the first reported solution that is capable of solving the real-time equations related to using ideal switch model and the associated circuitry in very small time-steps (e.g., an average of 36 ns in a three-phase back-to-back converter case study), without requiring large amount of memory, being limited to small number of switches, adding parasitic elements, or depending on a priori knowledge of the circuit operation or switching strategy. The accuracy of the proposed real-time simulator is verified against the results from experimental measurements. [ABSTRACT FROM AUTHOR]

Due to the repeated switching, the detailed switch-level models of electrical machines coupled with power-electronic converters are computationally expensive and hard to linearize for small-signal frequency-domain analysis. Average-value modeling (AVM) has become an effective tool for small-signal analysis of power electronic systems and time-domain transient studies where the details of switching are not important and can be neglected. Recently, a parametric AVM (PAVM) approach has been developed for machine/diode rectifier systems. This paper extends the parametric approach to the machine/thyristor-controlled-rectifier systems, where the thyristor firing may be referenced to either the line voltages or the rotor position. An analytical average model for this system is also developed based on the recently proposed constant-parameter voltage-behind-reactance synchronous machine model. The new PAVM is compared against the original switching system, as well as the analytical AVM. It is shown that the PAVM can accurately predict both small-signal characteristics and large-signal transients of the original switching system in light and heavy modes, which represents an advantage over the analytical models which are typically implicit. [ABSTRACT FROM AUTHOR]

In this paper, we review relevant problems in the modeling of dc–dc converters with switched capacitors. We study several approaches that overcome the exposed modeling difficulties, addressing ideal and nonideal cases and using dynamic equations that are valid in a large-signal domain. [ABSTRACT FROM PUBLISHER]

The model of a modular multilevel converter (MMC) determines the extent of critical circuit information that electromagnetic transient simulations can reveal. In this paper, two MMC models are proposed for efficient real-time hardware-in-the-loop (HIL) emulation on the field-programmable-gate-arrays (FPGA). The nonlinear switch-based model employing the insulated-gate bipolar transistor (IGBT) dynamic curve-fitting model considers factors affecting its transient performance so that device-level behavior such as power loss and junction temperature can be reproduced accurately in the electro-magnetic-thermal simulation of a power converter for its design evaluation. Meanwhile, regarding the MMC submodule as a transmission line stub achieves faster computation speed and enables the formation of a hybrid arm to save FPGA hardware resources. As the large network that the MMC presents is burdensome for real-time execution with a small time-step, circuit simplification based on partitioning and merging is conducted. Hardware implementation of a three-terminal high-voltage direct-current system containing an MMC-based dc–dc converter is carried out and the efficacy of proposed models is validated by comparing HIL emulation results with the offline simulation tool PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

This paper proposes a series of proactive hybrid high-voltage direct-current (HVDC) breaker (HHB) electromagnetic transient models that can be implemented in hardware-in-the-loop (HIL) emulation for real-time execution on the field-programmable gate array (FPGA). To achieve high fidelity, an HHB model should have the same configuration as the real one, and three different models for an insulated-gate bipolar transistor (IGBT), i.e., a two-state switch model, a curve-fitting model, and an improved nonlinear behavioral model, are proposed to satisfy different accuracy and simulation speed requirements. Since designing an HHB with hundreds of IGBTs in a massive array would lead to an extremely heavy computational burden as well as to a high FPGA resource utilization, circuit partitioning is applied to each model, which enables decomposition into a number of physically independent subcircuits with smaller matrix dimension to exploit parallel implementation. Meanwhile, low hardware resource demand is achieved by using one of the subcircuits to represent the rest since they are identical. As the IGBTs produce a significant amount of heat, which in turn affects their performance, an electrothermal network is added as part of the model to provide specific information about the device's operation status including the junction temperature. The models are applied to a three-terminal HVDC system, where line faults are simulated to activate HHB protection sequence. Comparison of device-level and system-level performance from HIL emulation with those of commercial offline simulation tools validates the accuracy of the proposed models as well as the efficacy of the solution approach. [ABSTRACT FROM AUTHOR]

Cellular automata (CAs) have been widely used to model and simulate physical systems and processes. CAs have also been successfully used as a VLSI architecture that proved to be very efficient at least in terms of silicon-area utilization and clock-speed maximization. Quantum cellular automata (QCAs) as one of the promising emerging technologies for nanoscale and quantum computing circuit implementation, provides very high scale integration, very high switching frequency and extremely low power characteristics. In this paper we present a new automated design architecture and a tool, namely DATICAQ (Design Automation Tool of 1-D CAs using QCAs), that builds a bridge between 1-D CAs as models of physical systems and processes and 1-D QCAs as nanoelectronic architecture. The QCA implementation of CAs not only drives the already developed CAs circuits to the nanoelectronics era but improves their performance significantly. The inputs of the proposed architecture are CA dimensionality, size, local rule, and initial and boundary conditions imposed by the particular problem. DATICAQ produces as output the layout of the QCA implementation of the particular 1-D CA model. Simulations of CA models for zero and periodic boundary conditions and the corresponding QCA circuits showed that the CA models have been successfully implemented. [ABSTRACT FROM PUBLISHER]

At a certain level of abstraction, power converters can be represented as linear circuits connected to diodes and controlled electronic switches. The evolutions of the electrical variables are determined by the state-dependent switchings, which complicate the mathematical modeling of controlled power converters. Differently from the complementarity models previously presented in the literature, the model proposed in this paper allows to represent as a linear complementarity system also closed-loop power converters, without requiring the a priori knowledge of the converter modes. A model construction procedure, not dependent on the specific converter topology, is presented. The discretization of the continuous-time model allows to formulate mixed linear complementarity problems for the computation of the control-to-output frequency response and the evolutions of both transient and steady-state currents and voltages. As illustrative examples, Z-source, boost, and buck dc-dc power converters under voltage-mode control and current-mode control operating both in continuous and discontinuous conduction modes are considered. [ABSTRACT FROM AUTHOR]

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current–voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools. [ABSTRACT FROM AUTHOR]

This article compares five modeling methods of grid-tied inverters for the electromagnetic transient simulation of power system, clarifies their differences, and discusses the suitable model for each simulation purpose. The comparison was made under the same conditions between the conventional switching model, and four simplified models—voltage interpolation, average-value, controlled current-injection, and simplified current-injection model. The comparison of the simulated waveforms clarifies the behaviors that can be simulated and cannot be simulated by each simplified model. The comparison of the computing time reveals the significant decrease of the computing time by selecting the proper simplified modeling method. Based on these comparisons, this article discusses the selection of the modeling methods for each simulation purpose to perform simulations accurately and efficiently. [ABSTRACT FROM AUTHOR]

In this article, we propose a new behavioral modeling method to reduce the running complexity and power consumption of digital predistortion (DPD) models for radio frequency power amplifiers. By employing the proposed method, different cross terms in a DPD model can be switched dynamically in real time. Each cross-term branch can further choose the model coefficients from multiple coefficient sets, which improves the DPD performance with little extra complexity. The switch of both cross-term branches and model coefficients is realized using a decision tree-based switch controller, leading to very low run-time complexity. By optimizing the selection process, different input samples can choose the most suitable model configuration that contributes most to the linearization performance. As only one branch is activated at a time, the power consumption can be greatly reduced. Based on the experimental results, the proposed method can achieve excellent linearization performance with significantly reduced power consumption. [ABSTRACT FROM AUTHOR]

The effect of splitter plates (SP) on current interruption at medium voltage (MV) level is theoretically investigated in the framework of Mayr's arc model, which is generalized to take into account the electrode fall voltage, V0, of the SP. The model is analytically solved in the current zero (CZ) region where the current (before CZ) and the voltage (after CZ) can be linearized with respect to time. The current turns out to be successfully interrupted if the total electrode fall voltage, NV0, for N − 1 SP plus contact electrodes, is larger than twice the transient recovery voltage, ${\boldsymbol{U}} \approx {\dot{\boldsymbol{U}t}}$ , at the characteristic arc decay time, t = τ, after CZ: ${\boldsymbol{N}}{{\boldsymbol{V}}_0} > 2{\dot{\boldsymbol{U}\tau }}$. For ${\boldsymbol{N}}{{\boldsymbol{V}}_0} < 2{\dot{\boldsymbol{U}\tau }}$ , an additional thermal condition must be satisfied, where also the current rate, ${\dot{\boldsymbol{I}}} = {\boldsymbol{\ dI}}/{\boldsymbol{dt}}$ before CZ, and the arc cooling power, K, are involved. The intuitive results lead to a simple understanding of the electrical effect of SP on current interruption at MV and serve as an initial design rule for the number of SP in different gases. [ABSTRACT FROM AUTHOR]

This article presents a dynamic averaged model of active neutral point clamped inverter (ANPCI). The proposed model helps in significant reduction of computational resources required for system-level studies in various applications which employ ANPCI as main power conversion stage. The average model derived in this article can consider the effect of various nonidealities in ANPCI, and also its capacitor voltage-balancing issues. The model is also modular in nature, i.e., it can be extended for an N-level ANPCI. PSCAD/EMTDC simulations and experiments are performed for steady-state and transient conditions to show that the averaged model developed in this article accurately predicts the steady-state and dynamic waveforms of ANPCI in both open-loop and closed-loop operations, even for large simulation time-steps. For the closed-loop operation, synchronous reference frame $dq$ -based controller is developed and implemented in a digital signal processor. In addition, the strength of the model is demonstrated by comparing the simulation waveforms and computational times required for simulating an ANPCI-based solar PV system using switching circuit model and the proposed averaged model. [ABSTRACT FROM AUTHOR]

Lumped-element grids provide an attractive option for wave propagation control in electromagnetic compatibility (EMC) engineering. This article investigates the peak shielding effectiveness (SE) of a diode grid used for protection of enclosures with apertures against high-intensity radiation fields (HIRFs). The nonlinearly loaded aperture is investigated with an efficient hybrid field-circuit simulation approach. Numerical experiments show that design aspects, e.g., aperture and enclosure size, grid density, impedance characteristic of lumped loads, play an important role in the field transmission through a diode grid which is nonlinear and time-variant. With a physics-based analysis of the interaction between the grid and the enclosure-backed aperture, nonlinear shielding techniques are identified that allow a control of the peak SE between 0 and 26 dB in novel ways. For the first time, the peak SE curve of a diode grid is demonstrated with four different field intensity dependencies, i.e., intensity low-pass, intensity high-pass, intensity bandpass, and intensity band-stop selectivities from tens V/m to hundreds of V/m. By considering design aspects into a two-step optimization procedure, practical guidelines are provided for the nonlinear shielding implementation. [ABSTRACT FROM AUTHOR]

Due to their salient features, modular multilevel converters (MMCs) are particularly suitable for a high-voltage direct current (HVDC) transmission system. Nevertheless, for an HVDC system, each phase of the MMC terminal may consist of several hundreds of submodules. This imposes a particular challenge in terms of steady-state simulation and modeling. Steady-state modeling is usually needed for determining the operating point for the MMC controller design and for predicting harmonics propagation in a power network. In this article, an efficient and accurate steady-state model for an MMC system with high-voltage levels is proposed. The model is based on a model reduction technique, namely residual-time restarting Krylov subspace method. As will be shown in this article, the proposed method is able to model various MMC systems. The results obtained from the proposed model are highly agreeable with those from PSCAD/EMTDC. Moreover, it will also be shown that the proposed method can drastically reduce the computation time for obtaining steady-state solutions. [ABSTRACT FROM AUTHOR]

Many power management algorithms demand accurate and fine-grained runtime estimations of dynamic core power. In the absence of fine-grained power sensors, model-based estimations are needed. Such power models commonly approximate the switching activity of logic gates using performance counters while assuming a linear performance counter/power relation at a fixed frequency and voltage. It has been shown that this relation cannot be captured accurately enough with purely linear models and that well-established nonlinear modeling techniques, e.g., polynomial modeling, easily overfit the underlying performance/power relations. Although neural-network-based modeling has shown to accurately capture nonlinear relations, it has a large training and inference overhead which is too high for fine-grained models on core-level and estimation rates in the range of 1–10 kHz. We propose a methodology for nonlinear transformation of specific performance counters to increase power modeling accuracy at constant frequency and voltage with a relatively low overhead for both model generation and run-time application over a linear model. Furthermore, we use least-angle regression (LARS) to determine a ranking of the performance counter inputs for use in linear and nonlinear modeling and show that the transformed performance counters are better suited for power modeling. The generated dynamic power model consisting of a nonlinear transformation block and a linear regression block reduces relative estimation error on average by 4% and in worst-case scenarios by 7% compared to state-of-the-art fine-grained linear power models. Compared to a state-of-the-art polynomial regression model our proposed approach reduces the relative estimation error by 10% in worst-case scenarios. [ABSTRACT FROM AUTHOR]

This article presents an innovative technique for the black-box modeling of the conductive emissions of switching circuits from external observations. The proposed methodology relies on the robust and elegant theory of periodically switched linear systems, providing the user with a tool for the generation of frequency-domain augmented linear time-invariant equivalents. The obtained models offer both a remarkable accuracy for different supply conditions and a deep understanding of the inherent switching mechanisms of this class of devices. The proposed framework also enables the derivation of a simplified enhanced Norton representation which outperforms the classical state-of-the-art models based on linear time-invariant approximations. Model parameters are computed via a blind procedure based only on two measurements. The feasibility and strength of the proposed approach are demonstrated on a dc–dc boost power converter and on a dc electrical motor via the prediction of their conducted disturbances. [ABSTRACT FROM AUTHOR]

The deployment of IoT has brought on the generation of massive amounts of data in need of analysis. In recent times, resistive switching-based crossbar arrays have been presented as a viable candidate for the acceleration of neural network inference, in pushing beyond the limit of CMOS process scaling so as to keep pace with the ever-growing complexity of computation. While plenty of empirical and physically descriptive models exist, their simulation run times become inconvenient for users when used in large scale crossbar arrays. In this brief, we first present a behavioral model of digital resistive switching devices, demonstrated on experimental PCM data to exhibit generality which can see useful implementation in circuit analysis methods for compute-in-memory applications. This model is based on a pair of nonlinear ordinary differential equations that request switching time and threshold voltage inputs from the user, which are the most important concerns for binarized weights in crossbar arrays. By stripping the model of detailed physical characteristics that is not required at the systems level, we demonstrate an improvement of computational run time of up to 20-fold over state-of-the-art physics-based models, and 1.3 times over the most commonly used empirically driven models. [ABSTRACT FROM AUTHOR]

To accurately capture the dynamics of a large-scale ac/dc system as a whole and the interactions between its individual components, a simulation method with high precision and efficiency is in great demand. For this purpose, we develop a multi-domain co-simulation method, in which the target system is partitioned into multiple dc and ac subsystems, represented by our proposed shifted-frequency phasor (SFP) models and the traditional EMT models, respectively. SFP models can be simulated with a much larger time step, leading to a significant improvement in simulation efficiency under a given requirement of precision. Further, a new interface model, namely, hybrid multi-domain transmission-line model (HMD-TLM), is developed to reflect the interactions between SFP models and EMT models, with the additional benefit of producing instantaneous and phasor waveforms simultaneously. Thus, the multi-domain co-simulation is implemented based on the efficient SFP models, the HMD-TLM, and a designed time sequences of simulation. The performance (efficiency and accuracy) of the proposed method has been validated on the well-known CIGRE ac/dc system as well as a practical system integrating large ac grids and modular-multilevel-converter-based multi-terminal dc grids. [ABSTRACT FROM AUTHOR]