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This paper introduces physics-based stripline ports for a segmented optimization of component footprints on printed circuit boards (PCBs). A segmentation is used for dividing a digital communication system into well-defined parts that are considered to be mostly independent. This technique is widely used in conjunction with generic 3-D electromagnetic field solvers, but it is new to physics-based models that until now only allow for ports at the upper and lower via ends, i.e., on PCB surfaces. Evidence of feasibility is provided by means of correlation with measurements and full-wave simulations up to 40 GHz. Since physics-based models can efficiently capture and simulate even systems of thousands of elements within acceptable computation time, the results of a segmented simulation can easily be compared to the full-board environment. The corresponding results are correlated to investigate limitations. [ABSTRACT FROM AUTHOR]

The aim of this paper is to present a six-phase induction machine (6PIM) model based on the so-called circuit-oriented approach suitable for simulation of electrical faults on both stator and rotor sides. This specific model has been developed by using only resistances, inductances, and controlled voltage sources. The coupling effects between both the stator and the rotor have been taken into account by the computation of stator–rotor mutual inductances. The model has been developed under the MATLAB/Simulink environment in order to have a universal tool that is easy to use with any control techniques. With this model, it is possible to simulate any type of electrical faults during the motion by closing or opening corresponding switches. The performances of the model have been validated by comparing simulation and experimental results of a 90-W 14-V 50-Hz two-pole 6PIM operating with different levels of load torque in healthy and faulty modes. Furthermore, this model has been associated to a fault-tolerant speed control method in phase opening occurrences in order to test the model accuracy. [ABSTRACT FROM AUTHOR]

Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process. [ABSTRACT FROM PUBLISHER]

Piezoelectric actuators (PEAs) have been widely used in nanotechnology due to their characteristics of fast response, large mass ratio, and high stiffness. However, hysteresis, which is an inherent nonlinear property of PEAs, greatly deteriorates the control performance of PEAs. In this paper, a nonlinear model predictive control (NMPC) approach is proposed for the displacement tracking problem of PEAs. First, a “nonlinear autoregressive–moving-average with exogenous inputs” (NARMAX) model of PEAs is implemented by multilayer neural networks; second, the tracking control problem is converted into an optimization problem by the principle of NMPC, and then, it is solved by the Levenberg–Marquardt algorithm. The most distinguished feature of the proposed approach is that the inversion model of hysteresis is no longer a necessity, which avoids the inversion imprecision problem encountered in the widely used inversion-based control algorithms. To verify the effectiveness of the proposed modeling and control methods, experiments are made on a commercial PEA product (P-753.1CD, Physik Instrumente), and comparisons with some existing controllers and a commercial proportional–integral–derivative controller are conducted. Experimental results show that the proposed scheme has satisfactory modeling and control performance. [ABSTRACT FROM PUBLISHER]

Unknown (X) values emerge during the design process as well as during system operation and test application. X-sources are for instance black boxes in design models, clock-domain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or binary decision diagram-based reasoning may fail to generate test patterns or to prove faults untestable. This paper proposes the first efficient stuck-at and transition-delay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal pessimism of conventional algorithms when X-values are considered by mapping the test generation problem to the SAT of quantified Boolean formulas. Experiments on ISCAS benchmarks and larger industrial circuits investigate the increase in fault coverage for conventional deterministic and potential detection requirements for both randomized and clustered X-sources. [ABSTRACT FROM PUBLISHER]

In this paper, the problem of geometry scaling of compact microwave structures is investigated. As opposed to conventional structures [i.e., constructed using uniform transmission lines (TLs)], re-design of miniaturized circuits (e.g., implemented with artificial TLs) for different operating frequencies is far from being straightforward due to considerable cross-couplings between the circuit components. Here, we develop a simple and computationally efficient methodology for dimension scaling of the compact circuits. The proposed approach utilizes an equivalent circuit representation to identify a fast inverse model that determines the relationship between the geometry parameters of the structure at hand and its operating frequency. Upon suitable correction, the inverse model is applied to find dimensions of the scaled design at the high-fidelity (electromagnetic (EM) simulation) model level. Owing to reasonable correlations between the low- and high-fidelity models, the circuit geometry scaled to a requested operating frequency can be found using just a single EM simulation of the structure, despite possible absolute discrepancies between the models. The proposed methodology is demonstrated using two exemplary compact couplers scaled in wide ranges from 0.5 to 2 GHz and from 0.5 to 1.8 GHz, respectively. The numerical results are supported by physical measurements of the fabricated coupler prototypes. [ABSTRACT FROM PUBLISHER]

In this paper, a new practical method is presented to estimate supercapacitor state for wireless sensor nodes. The self-discharge process of supercapacitor, as an energy storage device in sensor nodes, is usually considered as the main factor that needs to be taken into account for power management. Recent studies have demonstrated that a supercapacitor charge-redistribution process may also have significant impact on power management. To consider charge redistribution in power management of a real-time system, a practical method is presented to estimate the state of a supercapacitor. The accuracy of the method is validated by experiments. The impact of time step on the proposed model is also investigated. The results indicate that the proposed model can achieve good accuracy with relatively large time step. Moreover, the model is easy to implement, and has low memory usage and computational cost for practical applications in a real-time system. Based on the practical model, estimations of charge and energy transferred during the redistribution process are presented, which provide important information toward developing energy aware algorithms in wireless sensor networks. [ABSTRACT FROM AUTHOR]

This paper presents a generic hybrid optimization methodology based on space mapping techniques for the design of various high voltage pulse transformer structures used in klystron modulators. It is using two dimensioning models with different levels of complexity: a coarse model based on 2D FEA less accurate but cheaper to evaluate and a fine 3D FEA model more accurate but time consuming. A specific correction mechanism is applied to align the 2D FEA dimensioning model with the more accurate 3D FEA dimensioning model. With a suitable selection of the correction factors, the convergence of this hybrid optimal design methodology is obtained with a limited number of time consuming 3D FEA simulations. The method is applied to the optimal design of a monolithic high voltage pulse transformer for the CLIC klystron modulator. The influence of the klystron operating voltage on the size of the optimal pulse transformer is evaluated with the proposed design methodology. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of cell variability on the read performance of the one-selector one-resistor (1S1R) cross-point array. A variability-aware array-sizing analysis methodology is introduced, considering three independent variability sources, namely, the data pattern randomness, the selector variability, and the resistive switching element (RSE) variability. By analyzing the impact of each variability factor separately, we show that the data pattern randomness is not an important contributor for the read margin (RM) degradation. While the intrinsic RSE variability reflected in the narrowing of the ON/OFF RSE window degrades the RM, the selector variability adds to this further, mainly affecting the ON-state readout current, and causing extra RM degradation. To accommodate cell variability and guarantee acceptable read performance, additional cell performance margin is required. The 1S1R requirements are extrapolated for 1-Mb array, assuming variability-affected cells. It is found that, with a typical selector variability, a minimal RSE window of 5 and a selector half-bias nonlinearity of $\sim 8000$ are required to achieve at least 10% RM. [ABSTRACT FROM AUTHOR]

Superparamagnetic tunnel junctions (SMTJs) are noise powered stochastic oscillators, which can harness thermal energy through phenomena such as stochastic resonance and noise-induced synchronization. This enables them to operate with the minimal externally supplied energy, and therefore, makes them promising candidates for implementing bioinspired computing schemes. These applications require understanding how SMTJs can be integrated into CMOS circuits. In this paper, we present a compact model of SMTJ, written in the VerilogA language, that can be used within standard integrated circuit design tools. This compact model is based on the Néel–Brown model and allows for fast simulations. We show that this model can reproduce the experimental characterization of a sample subjected to different values of dc currents. Then, we definitively demonstrate the validity of the model by confronting it to the experimental results in the case of a complex phenomenon: noise-induced synchronization. [ABSTRACT FROM AUTHOR]

Multicore instruction-set simulation (MCISS) has become more and more important due to tremendous increase in number of multicore designs. To boost the speed of MCISS, one of the most effective and commonly used approaches is parallel simulation. However, timing synchronization must be applied to ensure accurate simulation results of parallel MCISS, and may induce huge synchronization overhead. In this paper, we propose a highly efficient and effective parallel MCISS approach by synchronizing timing before each synchronization function (SF) call. We improve the applicability of the state-of-the-art critical-section-level simulation approach with a generic blocking/nonblocking send/receive model covering all types of SFs. To further reduce synchronization overhead, we also introduce optimization methods such as a hybrid scheduling technique and provide an analysis algorithm that helps the designers to choose the host platform with the best simulation performance. Experiments show that the proposed approach attains a simulation speed of up to 285 MIPS, while producing accurate timing and functional results. [ABSTRACT FROM AUTHOR]

In this paper, an adjoint state-space dynamic neural network method for modeling nonlinear circuits and components is presented. This method is used for modeling the transient behavior of the nonlinear electronic and photonic components. The proposed technique is an extension of the existing state-space dynamic neural network (SSDNN) technique. The new method simultaneously adds the derivative information to the training patterns of nonlinear components, allowing the training to be done with less data without sacrificing model accuracy, and, consequently, makes training faster and more efficient. In addition, this method has been formulated such that it can be suitable for the parallel computation. The use of derivative information and parallelization makes training using the proposed technique much faster than the SSDNN. In addition, the models created using the proposed method are much faster to evaluate compared with the conventional models present in traditional circuit simulation tools. The validity of the proposed technique is demonstrated through the transient modeling of the physics-based CMOS driver, commercial NXP’s 74LVC04A inverting buffer, and nonlinear photonic components. [ABSTRACT FROM PUBLISHER]

Commercial photovoltaic (PV) modules are made of different PV cell technologies such as monocrystalline, multicrystalline, amorphous silicon, and copper indium diselenide. Usually, a single- or a double-diode PV model is used to model the output characteristic. However, it is unclear which PV model is optimal for each PV cell technology as the modeling accuracy is dependent on the PV model used. To fill up this research gap, a generalized multidimension $(n \times m)$ diode PV model is proposed in this paper to determine the optimal PV model. The proposed PV model allows the diode network to be configured to better fit the output characteristics of different PV cell technologies. Both simulation and experimental results are presented to illustrate the advantages of the proposed model. From the results, the optimal PV model that matches each of the cell technology is established. They can be used as a reference PV model for future works. [ABSTRACT FROM PUBLISHER]

This paper presents a general method for building equivalent electric circuits of power transformers, including eddy current effects in windings and core. A high-frequency equivalent dual model for single- and three-phase transformers with two multilayer windings is derived from the application of the principle of duality. The model is built from elements available in circuit simulation programs, such as Electromagnetic Transients Program (EMTP)–Alternative Transients Program, EMTP-RV, PSCAD, and PSpice. The parameters of the frequency-dependent leakage inductance and winding resistance are computed with analytical formulae obtained from the solution of Maxwell’s equations that are based on the geometrical dimensions and material information. Ideal transformers are utilized to isolate the electric components (winding resistors and capacitors) from the magnetic components (inductors). The physically correct connection points for electric and magnetic components are clearly identified. The proposed methodology is successfully validated versus finite- element simulations and laboratory measurements. [ABSTRACT FROM PUBLISHER]

To improve the efficiency of direct solution methods in SPICE-accurate integrated circuit (IC) simulations, preconditioned iterative solution techniques have been widely studied in the past decades. However, it is still an extremely challenging task to develop robust yet efficient general-purpose preconditioning methods that can deal with various types of large-scale IC problems. In this paper, based on recent graph sparsification research we propose circuit-oriented general-purpose support-circuit preconditioning (GPSCP) methods to dramatically improve the sparse matrix solution time and reduce the memory cost during SPICE-accurate IC simulations. By sparsifying the Laplacian matrix extracted from the original circuit network using graph sparsification techniques, general-purpose support circuits can be efficiently leveraged as preconditioners for solving large Jacobian matrices through Krylov-subspace iterations. Additionally, a performance model-guided graph sparsification framework is proposed to help automatically build nearly-optimal GPSCP solvers. Our experiment results for a variety of large-scale IC designs show that the proposed preconditioning techniques can achieve up to 18 \times runtime speedups and 7 \times memory reduction in DC and transient simulations when compared to state-of-the-art direct solution methods. [ABSTRACT FROM PUBLISHER]

With the steady growth of chip complexity and shrinking feature size, multiple challenges are emerging for transistor level circuit simulation. Compact SPICE models are a fundamental part of circuit verification, serving as a bridge between the semiconductor design and foundry. It is also an integral part of SPICE simulators, which directly affects tool performance and therefore design schedule. While the advanced 3-D technology nodes deliver superior level of scalability, simulation cost is rapidly increasing due to the computational complexity introduced by device model equations and the number of iterations required for numerical methods. In this paper, an efficient solution is proposed to reduce the computational cost associated with UC Berkeley BSIM-CMG device model evaluation, by applying robust Verilog compiler and computer algebra techniques to the device model equations. As a result of this implementation, simulation time reduction is up to 72% for complex blocks of the latest generation processor design. [ABSTRACT FROM PUBLISHER]

This paper proposes a numerical solution of the nonlinear equations that describes the hysteretic behavior of ferromagnetic materials. From the proper definition and solution of these equations, an equivalent circuit model for a ferromagnetic core is developed and proposed. The results obtained from the equivalent circuit are compared with those obtained by a rigorous numerical solution. [ABSTRACT FROM AUTHOR]

In this paper, we propose an efficient oscillation-diminishing cubic Hermite spline interpolation method for the table-based transistor model approximation. We use the cubic Hermite spline interpolation to ensure the continuity of the derivatives. Oscillation-diminishing techniques are proposed to reduce the oscillations (bumps) of interpolations such that both convergence and accuracy are significantly improved. Further, the oscillation-diminishing schemes do not rely on any real derivatives. Therefore, the proposed method can be used to build table models from measured data of the physical devices, where the real derivatives are not always available. In the proposed method, an adaptive approach is employed to generate the nonuniform interpolation grids such that the interpolation accuracy is guaranteed and the memory requirement is minimized. We also propose a novel combined exponential extrapolation method for off-state (leakage) current, which exactly follows the exponential-decay characteristic of that current. Test simulations on several classic industrial analog and mixed-signal circuits show that the proposed method can achieve high accuracy with lower computational cost compared with existing table-based model approximation methods. [ABSTRACT FROM PUBLISHER]

Cellular automata (CAs) have been widely used to model and simulate physical systems and processes. CAs have also been successfully used as a VLSI architecture that proved to be very efficient at least in terms of silicon-area utilization and clock-speed maximization. Quantum cellular automata (QCAs) as one of the promising emerging technologies for nanoscale and quantum computing circuit implementation, provides very high scale integration, very high switching frequency and extremely low power characteristics. In this paper we present a new automated design architecture and a tool, namely DATICAQ (Design Automation Tool of 1-D CAs using QCAs), that builds a bridge between 1-D CAs as models of physical systems and processes and 1-D QCAs as nanoelectronic architecture. The QCA implementation of CAs not only drives the already developed CAs circuits to the nanoelectronics era but improves their performance significantly. The inputs of the proposed architecture are CA dimensionality, size, local rule, and initial and boundary conditions imposed by the particular problem. DATICAQ produces as output the layout of the QCA implementation of the particular 1-D CA model. Simulations of CA models for zero and periodic boundary conditions and the corresponding QCA circuits showed that the CA models have been successfully implemented. [ABSTRACT FROM PUBLISHER]

Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. An accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional model based on one double-exponential source can be incomplete. A small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. The parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell. [ABSTRACT FROM AUTHOR]

The proper modeling of the transient thermal behavior of mutual heating effects between underground power cables is very important for the rating of transmission and distribution cables. The IEC standards proposed an accurate model based on exponential integrals that it can be difficult to implement in basic electrical software. The model is not consistent with the layered modeling of the cable thermal resistances. In this paper, a simple and easy-to-use alternative model is presented. It consists of injecting the correct current at the right position of the RC circuit representing the soil. The new model can accurately reproduce the full physics of the transient phenomenon and is consistent with the modeling of the cable used in the IEC standards themselves. The new model is tested and validated against numerous finite-element simulations for realistic cable installations. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100\boldsymbol \times faster than existing approaches and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with ≤5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints. [ABSTRACT FROM PUBLISHER]

Space mapping is a recognized method for speeding up electromagnetic (EM) optimization. Existing space-mapping approaches belong to the class of surrogate-based optimization methods. This paper proposes a cognition-driven formulation of space mapping that does not require explicit surrogates. The proposed method is applied to EM-based filter optimization. The new technique utilizes two sets of intermediate feature space parameters, including feature frequency parameters and ripple height parameters. The design variables are mapped to the feature frequency parameters, which are further mapped to the ripple height parameters. By formulating the cognition-driven optimization directly in the feature space, our method increases optimization efficiency and the ability to avoid being trapped in local minima. The technique is suitable for design of filters with equal-ripple responses. It is illustrated by two microwave filter examples. [ABSTRACT FROM PUBLISHER]

This paper analyzes short circuits in high-speed permanent-magnet (PM) machines. Analytical models are used to estimate the consequences of single-strand, parallel-strand, and phase-to-phase turn-to-turn short circuits, as well as open-circuit faults. The parameters for the analytical models are obtained from 3-D finite-element simulations and consider the actual position of each strand inside the slot. It is shown that parallel-strand short circuits are less severe than single-strand short circuits, both before and after fault mitigation actions. The potential for large fault current densities in high-speed PM machines is also demonstrated, with measured rms current densities up to 450 \A/mm^2 . A simple fault detector based on the synchronous detection of the machine and inverter neutral voltage difference is proposed, which is suitable for hardware implementation and can function as an independent observer of a drive system. The dependence of the detectability on the short circuit location and the effects of natural imbalances on the detector output are investigated. Experiments are performed to demonstrate the concept, showing that faults of at least 0.4% can be detected. [ABSTRACT FROM PUBLISHER]

Modeling partially shaded photovoltaic (PV) systems for online applications such as model-based MPPTs requires a PV circuit model with low computational time to simulate the large number of connected PV units within a reasonable amount of time. Unfortunately, the accurate PV models available in the literature are complex and suffer from high computational time due to their dependence on a transcendental implicit equation. This paper proposes a photovoltaic circuit model featuring lower computational time and comparable accuracy. The model utilizes the accuracy of the practical PV model and reduces the computational time by replacing the model series resistance with a third-degree-polynomial voltage-dependent source. The proposed model mimics the accurate characteristics of the practical model without being dependent on a transcendental implicit equation, thus providing low computational time. The model also introduces a new parameter to enhance the model's accuracy at low irradiance. The effectiveness of the model is shown by comparing the computational time and accuracy of the proposed model with those of the available models. A case study of partially shaded PV systems shows that the percentage of reduction in computational time improves with increases in the number of PV units in a simulated PV system, providing a clear advantage when simulating large PV systems. [ABSTRACT FROM PUBLISHER]

The realm of hardware-in-the-loop simulation resorts to field-programmable gate arrays to achieve time steps below 1 \mu\s . Such low time steps are of importance for the aerospace and automotive industries, where power converters have their switching frequencies in the 10- to 200-kHz range. This paper proposes a network tearing technique that allows subsets of switches to be treated independently, alleviates embedded memory requirements, and reduces the computational burden. An iterative algorithm is used to determine the state of naturally commutated switches, thus offering a realistic model of the power converter, independently of its operation mode or topology. A Gauss-Jordan processing unit is implemented to solve interface voltages/currents from the torn circuit. Custom floating-point operators are used to ensure good accuracy, high-frequency operation, and low computational latency. A neutral-point-clamped converter case study is presented to demonstrate the effectiveness of the method. Simulation results are validated against a reference model at a 750-ns time step and a 30-kHz sine pulsewidth modulation switching frequency. [ABSTRACT FROM PUBLISHER]

Low-watt compact fluorescent lamps (CFLs) may account for significant energy consumption of power distribution feeders in future years. This can lead to power-quality concerns because these devices consume highly distorted currents. In order to predict CFL harmonic current emissions into networks, CFL models capable of predicting these emissions accurately are being studied. On the other hand, these models require great computational effort in large-scale CFL penetration studies. This paper presents and discusses several approximate CFL models based on the harmonic-coupled admittance matrix model which reduces the computational effort while maintaining reasonable accuracy. The performance of the models is validated with CFL laboratory measurements. [ABSTRACT FROM AUTHOR]

Shared-memory chip-multiprocessor (CMP) architectures define memory consistency models that establish the ordering rules for memory operations from multiple threads. Validating the correctness of a CMP’s implementation of its memory consistency model requires extensive monitoring and analysis of memory accesses while multiple threads are executing on the CMP. In this paper, we present a low overhead solution for observing, recording and analyzing shared-memory interactions for use in an emulation and/or post-silicon validation environment. Our approach leverages portions of the CMP’s own data caches, augmented only by a small amount of hardware logic, to log information relevant to memory accesses. After transferring this information to a central memory location, we deploy our own analysis algorithm to detect any possible memory consistency violations. We build on the property that a violation corresponds to a cycle in an appropriately defined graph representing memory interactions. The solution we propose allows a designer to choose where to run the analysis algorithm: 1) on the CMP itself; 2) on a separate processor residing on the validation platform; or 3) off-line on a separate host machine. Our experimental results show an 83% bug detection rate, in our testbed CMP, over three distinct memory consistency models, namely: relaxed-memory order, total-store order, and sequential consistency. Finally, note that our solution can be disabled in the final product, leading to zero performance overhead and a per-core area overhead that is smaller than the size of a physical integer register file in a modern processor. [ABSTRACT FROM PUBLISHER]

In this paper, the conventional physics-based via (PBV) model is extended to multilayer substrate integrated waveguide (SIW) structures with via feeds. Furthermore, a novel PBV model for a more efficient modeling of multilayer SIW is proposed. This novel method allows to describe SIWs as transmission lines and to model the coupling between the layers with an equivalent circuit near-field model. Both PBV models are compatible and can be combined within a framework for modeling complex multilayer SIWs in an efficient manner. Results obtained by both methods are compared with full-wave solver results and show very good agreement from below cutoff frequency to about three times the cutoff frequency as well as a speed up of several orders of magnitude. [ABSTRACT FROM PUBLISHER]

A new semi-physical memoryless computationally effective behavioral model (BM) capable of predicting amplitude-modulation-to-amplitude-modulation (AM–AM) and amplitude-modulation-to-phase-modulation (AM–PM) distortions is proposed. In recent years, AM–AM and AM–PM distortions have been separately studied in literature. Here, we investigate the correlation between AM–AM and AM–PM distortions first. Based on the observed correlation, a novel AM–PM model is derived from the well-known Rapp AM–AM model. On the basis of the close relationship between the AM–AM and AM–PM model, a highly accurate and computationally effective large-signal BM is obtained. The newly developed model addresses the current needs of the mobile industry that requires BMs of the power amplifier (PA), which can be interpreted by the designers. In addition, the models must be computationally effective due to the limited computation power in mobile handset. Therefore, only memoryless BMs can be taken into account and larger errors are accepted for the sake of computational effectiveness. In this paper, it is shown that the newly introduced model achieves excellent results, when it is applied to actual industrial applications of two GaAs-based class-AB PAs in 65-nm technology and one CMOS-based class AB PA in 28-nm technology, which are designed for mobile communications. [ABSTRACT FROM PUBLISHER]

Due to the repeated switching, the detailed switch-level models of electrical machines coupled with power-electronic converters are computationally expensive and hard to linearize for small-signal frequency-domain analysis. Average-value modeling (AVM) has become an effective tool for small-signal analysis of power electronic systems and time-domain transient studies where the details of switching are not important and can be neglected. Recently, a parametric AVM (PAVM) approach has been developed for machine/diode rectifier systems. This paper extends the parametric approach to the machine/thyristor-controlled-rectifier systems, where the thyristor firing may be referenced to either the line voltages or the rotor position. An analytical average model for this system is also developed based on the recently proposed constant-parameter voltage-behind-reactance synchronous machine model. The new PAVM is compared against the original switching system, as well as the analytical AVM. It is shown that the PAVM can accurately predict both small-signal characteristics and large-signal transients of the original switching system in light and heavy modes, which represents an advantage over the analytical models which are typically implicit. [ABSTRACT FROM AUTHOR]

This paper presents photovoltaic-oriented nodal analysis (PVONA), a general and flexible tool for efficient spatially resolved simulations for photovoltaic (PV) cells and modules. This approach overcomes the major problem of the conventional Simulation Program with Integrated Circuit Emphasis-based approaches for solving circuit network models, which is the limited number of nodes that can be simulated due to memory and computing time requirements. PVONA integrates a specifically designed sparse data structure and a graphics processing unit-based parallel conjugate gradient algorithm into a PV-oriented iterative Newton–Raphson solver. This first avoids the complicated and time-consuming netlist parsing, second saves memory space, and third accelerates the simulation procedure. In the tests, PVONA generated the local current and voltage maps of a model with $316 \times 316$ nodes with a thin-film PV cell in 15 s, i.e., using only 4.6% of the time required by the latest LTSpice package. The 2-D characterization is used as a case study and the potential application of PVONA toward quantitative analysis of electroluminescence are discussed. [ABSTRACT FROM AUTHOR]

Defects or traps in semiconductors and nano devices that randomly capture and emit charge carriers result in low-frequency noise, such as burst and $1/f$ noise, which are important concerns in the design of both analog and digital circuits. The capture and emission rates of these traps are functions of the time-varying voltages across the device, resulting in nonstationary noise characteristics. Modeling of low-frequency, nonstationary noise in circuit simulators is a long-standing open problem. It has been realized that the low-frequency noise models in circuit simulators were the culprits that produced erroneous noise performance results for circuits under strongly time-varying bias conditions. In this paper, we present two fully nonstationary models for traps, a fine-grained Markov chain model and a coarse-grained Langevin model based on similar models for ion channels in neurons. The nonstationary trap models we present subsume and unify all of the work that has been done recently in the device modeling and circuit design literature on modeling nonstationary trap noise. We provide a detailed explication of these models with regard to their stochastic properties and develop carefully crafted circuit simulation techniques that are stochastically correct. We have implemented the proposed techniques in a MATLAB-based circuit simulator, by expanding the industry standard compact MOSFET model PSP to include a nonstationary description of oxide traps. We present results obtained by this extended model and the proposed simulation techniques for the low-frequency noise characterization of a common source amplifier and the phase jitter of a ring oscillator. [ABSTRACT FROM PUBLISHER]

Recently, most background modeling approaches represent distributions of background changes by using parametric models such as Gaussian mixture models. Because of significant illumination changes and dynamic moving backgrounds with time, variations of background changes are hard to be modeled by parametric background models. Moreover, how to efficiently and effectively update parameters of parametric models to reflect background changes remains a problem. In this paper, we propose a novel coarse-to-fine detection theory algorithm to extract foreground objects on the basis of nonparametric background and foreground models represented by binary descriptors. We update background and foreground models by a first-in–first-out strategy to maintain the most recent observed background and foreground instances. As shown in the experiments, our method can achieve better foreground extraction results and fewer false alarms of surveillance videos with lighting changes and dynamic backgrounds in both collected and CDnet 2012 benchmark data sets. [ABSTRACT FROM AUTHOR]

This paper proposes the use of coupled electric and magnetic circuits in the schematic models of high frequency integrated circuits, as an effective method to model the global inductive effects and coupling. These pairs of coupled circuits, called magneto-electro-equivalent circuit (MEEC) models, are obtained by partitioning the computational domain into several subdomains, each having its own electromagnetic field regime. The model reduction method we propose can be used not only to derive the full coupled electric and magnetic circuit model of a device starting from its layout, but also to correct the electric schematic by adding inductive parasitic effects. The MEEC approach uses special boundary conditions—called magnetic/electric hooks—on the interfaces between the subparts in which the computational domain is partitioned. The success of the correct extraction of inductive effects rely on the terminal reduction, i.e., the correct placement of magnetic hooks on the interfaces. In order to find this placement, a heuristic approach based on IC layout analysis is proposed. In order to consider the parasitic inductive couplings, the electric schematic circuit graph is enhanced with geometric information from the layout (e.g., node coordinates). The MEEC-based approach is validated for a real example of a low noise amplifier. Its initial layout design proved to be wrong only after the fabrication and characterization of the first prototype. The use of the inductive parasitic extraction tool, based on the MEEC approach, would have prevented this. MEEC is an alternative approach to vector potential equivalent circuit, with respect to which advantages and disadvantages are discussed. [ABSTRACT FROM PUBLISHER]

Power grid (PG) simulation is critical for analysis and verification of power supply noises for robust and reliable integrated circuit (IC) designs. Computational demands to simulate PG for ICs with increasing complexity is never-ending. Cloud computing platforms can be leveraged to mitigate costs associated with making these resources available. However, since simulation data usually contains sensitive design information, simulating on third-party platforms lead to major security concerns. In this paper, we propose a framework for secure PG simulation on Cloud. A transformation algorithm to hide current excitations is presented, while still allowing a majority of computations to be completed on Cloud. We employ multiple compression strategies to significantly reduce communication overheads. Experiments show that our framework can achieve similar turn-around time as an insecure simulator on Cloud, while securing current excitations and output voltage vectors with reasonable communication and computational overheads. [ABSTRACT FROM PUBLISHER]

Interfacing of electrical machine models with ac power networks has a significant impact on numerical accuracy and efficiency in state-variable-based transient simulation programs. This paper continues the recent work in this area by proposing a new explicit constant-parameter voltage-behind-reactance (VBR) induction machine model that includes main flux saturation and allows a direct interface to any external network. The proposed model uses numerical approximations to achieve a decoupled interfacing circuit with constant RL branches that is easy to use in many simulation programs. Computer studies demonstrate that the proposed model provides high numerical accuracy for machines with a diverse range of parameters, even at fairly large integration step sizes. [ABSTRACT FROM AUTHOR]

In this paper, we review relevant problems in the modeling of dc–dc converters with switched capacitors. We study several approaches that overcome the exposed modeling difficulties, addressing ideal and nonideal cases and using dynamic equations that are valid in a large-signal domain. [ABSTRACT FROM PUBLISHER]

Wide bandgap power devices have emerged as an often superior alternative power switch technology for many power electronic applications. These devices theoretically have excellent material properties enabling power device operation at higher switching frequencies and higher temperatures compared with conventional silicon devices. However, material defects can dominate device behavior, particularly over time, and this should be strongly considered when trying to model actual characteristics of currently available devices. Compact models of wide bandgap power devices are necessary to analyze and evaluate their impact on circuit and system performance. Available compact models, i.e., models compatible with circuit-level simulators, are reviewed. In particular, this paper presents a review of compact models for silicon carbide power diodes and MOSFETs. [ABSTRACT FROM AUTHOR]

The behavior of a grounding system can be predicted by using either the electrical equivalent circuit models or electromagnetic computation. Despite its advantages over the latter, the equivalent circuit model fails to accurately predict the behavior under transient conditions due to the absence of two key factors, namely: 1) the current rate-of-rise and 2) soil ionization. This paper proposes a method to enhance the performance of the equivalent circuit model by taking into consideration of both mentioned factors. It is discovered that by using the proposed method, the estimated values of R and L of the equivalent circuit model are improved. The computed inductance dynamically changes with the change in the lightning current parameters, thus improving its accuracy for all current rate-of-rise conditions. The soil ionization effect is implemented as recommended by CIGRE, and this further improves the accuracy of the model. As a result, the voltage response of the model becomes more accurate and comparable to the electromagnetic computation results. Another important feature of the proposed model is that it can be directly applied or connected to power system equipment. Thus, an accurate grounding system effect on the transient performance of key power equipment, such as surge arresters, can be obtained. [ABSTRACT FROM PUBLISHER]

Computational intelligence techniques are used to approximate the nonlinear operation of \LiFePO4 batteries using rule-based systems. In this paper, rule-based systems are not directly fitted to data, but comprise constructive blocks in a differential-equation-based dynamical model that is numerically integrated to infer battery voltage, charge, and temperature. The design methodology has been validated with three different \ \hspace*-1.8ptLiFePO4 batteries, and the results were found to be more accurate than those of a selection of statistical models and state-of-the-art artificial intelligence techniques. [ABSTRACT FROM PUBLISHER]